SPRSPA3A March 2024 – September 2024 AM67 , AM67A
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
This section describes connectivity requirements for package balls that have specific connectivity requirements and unused package balls.
All power pins must be supplied with the voltages specified in Recommended Operating Conditions, unless otherwise specified.
For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be connected to these device ball numbers.
AMW BALL NUMBER |
BALL NAME | CONNECTION REQUIREMENTS |
---|---|---|
B10 | TRSTn | Each of these balls must be connected to VSS through separate external pull resistors to ensure these balls are held to a valid logic-low level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-down can be used to hold a valid logic-low level if no PCB signal trace is connected to the ball. |
A11 E12 F11 |
TCK TDI TMS |
Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic-high level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-up can be used to hold a valid logic-high level if no PCB signal trace is connected to the ball. |
C9 F9 D10 E26 E8 B23 B13 E11 B9 D11 F1 J1 U1 T1 |
EMU0 EMU1 MCU_RESETz RESET_REQz MCU_PORz EXTINTN MCU_I2C0_SCL MCU_I2C0_SDA WKUP_I2C0_SCL WKUP_I2C0_SDA DDR0_DQS0_n DDR0_DQS1_n DDR0_DQS2_n DDR0_DQS3_n |
Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic-high level, if unused. |
R22 R23 R26 T27 T25 T24 T21 T22 U27 U26 V27 V25 V26 V24 V22 V23 |
GPMC0_AD0 GPMC0_AD1 GPMC0_AD2 GPMC0_AD3 GPMC0_AD4 GPMC0_AD5 GPMC0_AD6 GPMC0_AD7 GPMC0_AD8 GPMC0_AD9 GPMC0_AD10 GPMC0_AD11 GPMC0_AD12 GPMC0_AD13 GPMC0_AD14 GPMC0_AD15 |
Each of these balls must be connected to the corresponding power supply(1) or VSS through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic-high or logic-low level as appropriate to select the desired device boot mode. |
E1 H1 T1 W1 G7 J7 K7 A3 |
DDR0_DQS0 DDR0_DQS1 DDR0_DQS2 DDR0_DQS3 VMON_ER_VSYS VMON_1P8_SOC VMON_3P3_SOC WKUP_LFOSC0_XI |
Each of these balls must be connected to VSS through separate external pull resistors to ensure these balls are held to a valid logic-low level, if unused. |
E15 F14 AB8 AA10 AB14 AB15 AA16 AA8 E18 |
SERDES0_REXT SERDES1_REXT CSI0_RXRCALIB CSI1_RXRCALIB CSI2_RXRCALIB CSI3_RXRCALIB DSI0_TXRCALIB USB0_RCALIB USB1_RCALIB |
Each of these balls must be connected to VSS through an appropriate external pull resistor to ensure these balls are held to a valid logic-low level, if unused. Refer to Signal Descriptions footnote for appropriate value of pull resistor for each signal. |
G9 AC1 |
VPP MMC0_CALPAD |
Each of these balls must be left unconnected, if unused. |
All other unused signal balls with a Pad Configuration Register can be left unconnected with their multiplexing mode set to GPIO input and internal pull-down resistor enabled. Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case where internal pull resistors are allowed as the only source/sink to hold a valid logic level. Any balls connected to a via, test point, or PCB trace are consider used and must not depend on the internal pull resistor to hold a valid logic level.
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This can be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors are recommended to hold a valid logic level on balls with external connections.
Many of the device IOs are turned off by default and external pull resistors may be required to hold inputs of any attached device in a valid logic state until software initializes the respective IOs. The state of configurable device IOs are defined in the BALL STATE DURING RESET RX/TX/PULL and BALL STATE AFTER RESET RX/TX/PULL columns of the Pin Attributes table. Any IO with its input buffer (RX) turned off is allowed to float without damaging the device. However, any IO with its input buffer (RX) turned on shall never be allowed to float to any potential between VILSS and VIHSS. The input buffer can enter a high-current state which could damage the IO cell if allowed to float between these levels.