SLUSCM3K June 2016 – July 2020 BQ77904 , BQ77905
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE | ||||||
| V(POR) | POR threshold | VDD rising, 0 to 6 V | 4 | V | ||
| V(SHUT) | Shutdown threshold | VDD falling, 6 to 0 V | 2 | 3.25 | V | |
| V(AVDD) | AVDD voltage | C(VDD) = 1 µF | 2.1 | 2.5 | 3.25 | V |
| SUPPLY AND LEAKAGE CURRENT | ||||||
| ICC | NORMAL mode current (bq77904/bq77905) | Cell1 through Cell5 = 4 V, VDD = 20 V (bq77905) | 6 | 9 | µA | |
| I(CFAULT) | Fault condition current | State comparator on | 8 | 12 | µA | |
| IOFF | SHUTDOWN mode current | VDD < VSHUT | 0.5 | µA | ||
| ILKG(OW_DIS) | Input leakage current at VCx pins | All cell voltages = 4 V, Open-wire disable configuration | –100 | 0 | 100 | nA |
| ILKG(100nA) | Open-wire sink current at VCx pins | All cell voltages = 4 V, 100-nA configuration | 30 | 110 | 175 | nA |
| ILKG(200nA) | Open-wire sink current at VCx pins | All cell voltages = 4 V, 200-nA configuration | 95 | 210 | 315 | nA |
| ILKG(400nA) | Open-wire sink current at VCx pins | All cell voltages = 4 V, 400-nA configuration | 220 | 425 | 640 | nA |
| PROTECTION ACCURACIES | ||||||
| VOV | Overvoltage programmable threshold range | 3000 | 4575 | mV | ||
| VUV | Undervoltage programmable threshold range | 1200 | 3000 | mV | ||
| V(VA) | OV, UV, detection accuracy | TA = 25°C, OV detection accuracy | –10 | 10 | mV | |
| TA = 25°C, UV detection accuracy | –18 | 18 | mV | |||
| TA = 0 to 60°C | –28 | 26 | mV | |||
| TA = –40 to 85°C | –40 | 40 | mV | |||
| VHYS(OV) | OV hysteresis programmable threshold range | 0 | 400 | mV | ||
| VHYS(UV) | UV hysteresis programmable threshold range | 200 | 800 | mV | ||
| VOTD | Overtemperature in discharge programmable threshold (ratio of VTB) | Threshold for 65°C(1) | 19.71% | 20.56% | 21.86% | V |
| Threshold for 70°C (1) | 17.36% | 18.22% | 19.51% | VTB | ||
| VOTD(REC) | Overtemperature in discharge recovery (ratio of VTB) | Recovery threshold at 55°C for when VOTD is at 65°C(1) | 25.24% | 26.12% | 27.44% | VTB |
| Recovery threshold at 60°C for when VOTD is at 70°C(1) | 22.12% | 23.2% | 24.24% | VTB | ||
| VOTC | Overtemperature in charge programmable threshold (ratio of VTB) | Threshold for 45°C(1) | 32.14% | 32.94% | 34.54% | VTB |
| Threshold for 50°C(1) | 29.15% | 29.38% | 31.45% | VTB | ||
| VOTC(REC) | Overtemperature in charge recovery (ratio of VTB) | Recovery threshold at 35°C when VOTD is at 45°C(1) | 38.63% | 40.97% | 40.99% | VTB |
| Recovery threshold at 40°C when VOTD is at 50°C(1) | 36.18% | 36.82% | 38.47% | VTB | ||
| VUTD | Undertemperature in discharge programmable threshold (ratio of VTB) | Threshold for –20°C(1) | 86.41% | 87.14% | 89.72% | VTB |
| Threshold for –10°C(1) | 80.04% | 80.94% | 83.10% | VTB | ||
| VUTD(REC) | Undertemperature in discharge recovery (ratio of VTB) | Recovery threshold at –10°C when VUTD is at –20°C(1) | 80.04% | 80.94% | 83.10% | VTB |
| Recovery threshold at 0°C when VUTD is at –10°C(1) | 71.70% | 73.18% | 74.86% | VTB | ||
| VUTC | Undertemperature in charge programmable threshold (ratio of VTB) | Threshold for –5°C(1) | 75.06% | 77.22% | 78.32% | VTB |
| Threshold for 0°C(1) | 71.70% | 73.18% | 74.86% | VTB | ||
| VUTC(REC) | Undertemperature in Charge Recovery (ratio of VTB) | Recovery threshold at 5°C when VUTC is at –5°C(1) | 68.80% | 69.73% | 71.71% | VTB |
| Recovery threshold at 10°C when VUTC is at 0°C(1) | 64.67% | 65.52% | 67.46% | VTB | ||
| VOCD1 | Overcurrent discharge 1 programmable threshold range, (VSRP – VSRN) | –85 | –10 | mV | ||
| VOCD2 | Overcurrent discharge 2 programmable threshold range, (VSRP – VSRN) | –20 | –170 | mV | ||
| VSCD | Short circuit discharge programmable threshold range, (VSRP – VSRN) | –40 | –340 | mV | ||
| VCCAL | OCD1 detection accuracy at lower thresholds | VOCD1 > –20 mV | –30% | 30% | ||
| VCCAH | OCD1, OCD2, SCD detection accuracy | VOCD1 ≤ –20 mV; all OCD2 and SCD threshold ranges | –20% | 20% | ||
| VOW | Open-wire fault voltage threshold at VCx per cell with respect to VCx-1 | Voltage falling on VCx, 3.6 V to 0 V | 450 | 500 | 550 | mV |
| VOW(HYS) | Hysteresis for open wire fault | Voltage rising on VCx, 0 V to 3.6 V | 100 | mV | ||
| CHARGE AND DISCHARGE FET DRIVERS | ||||||
| V(FETON) | CHG/CHGU/DSG on | VDD ≥ 12 V, CL = 10 nF | 11 | 12 | 14 | V |
| VDD < 12 V, CL = 10 nF | VDD – 1 | VDD | V | |||
| V(FETOFF) | CHG/CHGU/DSG off | No load when CHG/CHGU/DSG is off. | 0.5 | V | ||
| R(CHGOFF) | CHG off resistance | CHG off for > tCHGPDN and pin held at 2 V | 0.5 | kΩ | ||
| R(DSGOFF) | CHGU/DSG off resistance | CHGU/DSG off and pin held at 2 V | 10 | 16 | Ω | |
| ICHG(CLAMP) | CHG clamp current | CHG off and pin held at 18 V | 450 | µA | ||
| VCHG(CLAMP) | CHG clamp voltage | ICHG(CLAMP) = 300 µA | 16 | 18 | 20.5 | V |
| tCHGON | CHG on rise time | CL = 10 nF, 10% to 90% | 50 | 150 | µs | |
| tDSGON | CHGU/DSG on rise time | CL = 10 nF, 10% to 90% | 2 | 75 | µs | |
| tCHGOFF | CHG off fall time | CL = 10 nF, 90% to 10% | 15 | 30 | µs | |
| tDSGOFF | CHGU/DSG off fall time | CL = 10 nF, 90% to 10% | 5 | 15 | µs | |
| CTRC AND CTRD CONTROL | ||||||
| VCTR1 | Enable FET driver (VSS) | With respect to VSS. Enabled < MAX | 0.6 | V | ||
| VCTR2 | Enable FET driver (Stacked) | Enabled > MIN | VDD + 2.2 | V | ||
| VCTR(DIS) | Disable FET driver | Disabled between MIN and MAX | 2.04 | VDD + 0.7 | V | |
| VCTR(MAXV) | CTRC and CTRD clamp voltage | ICTR = 600 nA | VDD + 2.8 | VDD + 4 | VDD + 5 | V |
| tCTRDEG_ON)(2) | CTRC and CTRD deglitch for ON signal | 7 | ms | |||
| tCTRDEG_OFF(2) | CTRC and CTRD deglitch for OFF signal | 7 | ms | |||
| CURRENT STATE COMPARATOR | ||||||
| V(STATE_D1) | Discharge qualification threshold1 | Measured at SRP-SRN | –3 | –2 | –1 | mV |
| V(STATE_C1) | Charge qualification threshold1 | Measured at SRP-SRN | 1 | 2 | 3 | mV |
| tSTATE(2) | State detection qualification time | 1.2 | ms | |||
| LOAD REMOVAL DETECTION | ||||||
| VLD(CLAMP) | LD clamp voltage | I(LDCLAMP) = 300 µA | 16 | 18 | 20.5 | V |
| ILD(CLAMP) | LD clamp current | V(LDCLAMP) = 18 V | 450 | µA | ||
| VLDT | LD threshold | Load removed < when VLDT | 1.25 | 1.3 | 1.35 | V |
| RLD(INT) | LD input resistance when enabled | Measured to VSS | 160 | 250 | 375 | kΩ |
| tLD_DEG | LD detection deglitch | 1 | 1.5 | 2.3 | ms | |
| CCFG PIN | ||||||
| V(CCFGL) | CCFG threshold low (ratio of VAVDD) | 3-cell configuration | 10% | V | ||
| V(CCFGH) | CCFG threshold high (ratio of VAVDD) | 4-cell configuration | 65% | 100% | V | |
| V(CCFGHZ) | CFG threshold high-Z (ratio of VAVDD) | 5-cell configuration, CCFG floating, internally biased | 25% | 33% | 45% | V |
| tCCFG_DEG(2) | CCFG deglitch | 6 | ms | |||
| CUSTOMER TEST MODE (CTM) | ||||||
| V(CTM) | Customer test mode entry voltage at VDD | VDD > VC5 + V(CTM), TA = 25°C | 8.5 | 10 | V | |
| tCTM_ENTRY(3) | Delay time to enter and exit Customer Test Mode | VDD > VC5 + V(CTM), TA = 25°C | 50 | ms | ||
| tCTM_DELAY(3) | Delay time of faults while in Customer Test Mode | TA = 25°C | 200 | ms | ||
| tCTM_OC_REC(3) | Fault recovery time of OCD1, OCD2, and SCD faults while in Customer Test Mode | 1 s and 8 s options, TA = 25°C | 100 | ms | ||