SLUSCM3K June   2016  – July 2020 BQ77904 , BQ77905

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Device Functionality Summary
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Protection Summary
      2. 8.3.2  Fault Operation
        1. 8.3.2.1  Operation in OV
        2. 8.3.2.2  Operation in UV
        3. 8.3.2.3  Operation in OW
        4. 8.3.2.4  Operation in OCD1
        5. 8.3.2.5  Operation in OCD2
        6. 8.3.2.6  Operation in SCD
        7. 8.3.2.7  Overcurrent Recovery Timer
        8. 8.3.2.8  Load Removal Detection
        9. 8.3.2.9  Load Removal Detection in UV
        10. 8.3.2.10 Operation in OTC
        11. 8.3.2.11 Operation in OTD
        12. 8.3.2.12 Operation in UTC
        13. 8.3.2.13 Operation in UTD
      3. 8.3.3  Protection Response and Recovery Summary
      4. 8.3.4  Configuration CRC Check and Comparator Built-In-Self-Test
      5. 8.3.5  Fault Detection Method
        1. 8.3.5.1 Filtered Fault Detection
      6. 8.3.6  State Comparator
      7. 8.3.7  DSG FET Driver Operation
      8. 8.3.8  CHG FET Driver Operation
      9. 8.3.9  External Override of CHG and DSG Drivers
      10. 8.3.10 Configuring 3-S, 4-S, or 5-S Mode
      11. 8.3.11 Stacking Implementations
      12. 8.3.12 Zero-Volt Battery Charging Inhibition
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 Power-On Reset (POR)
        2. 8.4.1.2 FAULT Mode
        3. 8.4.1.3 SHUTDOWN Mode
        4. 8.4.1.4 Customer Fast Production Test Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Recommended System Implementation
        1. 9.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 9.1.1.2 Protecting CHG and LD
        3. 9.1.1.3 Protecting CHG FET
        4. 9.1.1.4 Using Load Detect for UV Fault Recovery
        5. 9.1.1.5 Temperature Protection
        6. 9.1.1.6 Adding Filter to Sense Resistor
        7. 9.1.1.7 Using a State Comparator in an Application
          1. 9.1.1.7.1 Examples
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Example
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.11 Stacking Implementations

Higher than 5-S cell packs may be supported by daisy-chaining multiple devices. Each device ensures OV, UV, OTC, OTD, UTC, and UTD protections of its directly monitored cells, while any fault conditions automatically disable the global CHG and/or DSG FET driver. Note that upper devices do not provide OCD1, OCD2, or SCD protections, as these are based on pack current. For the BQ77904 and BQ77905 devices used on the upper stack, the SRP and SRN pins should be shorted to prevent false detection.

Table 8-6 Stacking Implementation Configurations
CONFIGURATIONCHG PINCHGU PIN
Bottom or single deviceConnect to CHG FETLeave unconnected
Upper stackLeave unconnectedConnect to CTRC of the lower device

To configure higher-cell packs, follow this procedure:

  • Each device must have a connection on at least three lowest-cell input pins.
  • TI recommends to connect a higher-cell count to the upper devices (for example, for a 7-S configuration, connect four cells on the upper device and three cells on the bottom device). This provides a stronger CRTx signal to the bottom device.
  • Ensure that each device’s CCFG pin is configured appropriately for its specific number of cells (three, four, or five cells).
  • For the bottom device, the CHG pin should be used to drive the CHG FET and leave the CHGU pin unconnected. For the upper device, the CHGU pin should be used to connect to lower device’s CTRC pin with a RCTRx and leave the CHG pin unconnected.
  • Connect the upper DSG pins with a RCTRx to the immediate lower device CTRD pin.
  • All upper devices should have the SRP and SRN to its AVSS pin.
  • If load removal is not used for UV recovery, connect the upper device LD pin to its AVSS pin, as shown in Figure 8-9 and Figure 8-10. Otherwise, refer to Figure 9-7 for proper LD connection.
GUID-B64C4A6A-A36D-4D28-AC30-30C58D4EAF41-low.gifFigure 8-9 10S Pack Using Two BQ77905 Devices
GUID-BABAD813-457F-4FCF-90F1-A1E839321E14-low.gifFigure 8-10 13S Pack Using Three BQ77905 Devices