SLASEO0C July   2018  – August 2025 DAC61416 , DAC71416 , DAC81416

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Transfer Function
        2. 6.3.1.2 DAC Register Structure
          1. 6.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 6.3.1.2.2 Broadcast DAC Register
          3. 6.3.1.2.3 Clear DAC Operation
      2. 6.3.2 Internal Reference
      3. 6.3.3 Device Reset Options
        1. 6.3.3.1 Power-On Reset (POR)
        2. 6.3.3.2 Hardware Reset
        3. 6.3.3.3 Software Reset
      4. 6.3.4 Thermal Protection
        1. 6.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 6.3.4.2 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Toggle Mode
      2. 6.4.2 Differential Mode
      3. 6.4.3 Power-Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
        1. 6.5.1.1 Streaming Mode Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. 7 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.3.2 Hardware Reset

A device hardware reset event is initiated by a minimum 500 ns logic low on the RESET pin. A hardware reset initiates a POR event.