SLASEO0C July   2018  – August 2025 DAC61416 , DAC71416 , DAC81416

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Transfer Function
        2. 6.3.1.2 DAC Register Structure
          1. 6.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 6.3.1.2.2 Broadcast DAC Register
          3. 6.3.1.2.3 Clear DAC Operation
      2. 6.3.2 Internal Reference
      3. 6.3.3 Device Reset Options
        1. 6.3.3.1 Power-On Reset (POR)
        2. 6.3.3.2 Hardware Reset
        3. 6.3.3.3 Software Reset
      4. 6.3.4 Thermal Protection
        1. 6.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 6.3.4.2 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Toggle Mode
      2. 6.4.2 Differential Mode
      3. 6.4.3 Power-Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
        1. 6.5.1.1 Streaming Mode Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. 7 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SERIAL INTERFACE - WRITE OPERATION
f(SCLK) Serial clock frequency VIO = 1.7 V to 2.7 V 25 MHz
VIO = 2.7 V to 5.5 V 50
tSCLKHIGH SCLK high time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 10
tSCLKLOW SCLK low time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 10
tSDIS SDI setup time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tSDIH SDI hold time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tCSS CS to SCLK falling edge setup time VIO = 1.7 V to 2.7 V 30 ns
VIO = 2.7 V to 5.5 V 15
tCSH SCLK falling edge to CS rising edge VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tCSHIGH CS high time VIO = 1.7 V to 2.7 V 50 ns
VIO = 2.7 V to 5.5 V 25
tDACWAIT Sequential DAC update wait time VIO = 1.7 V to 2.7 V 2.4 µs
VIO = 2.7 V to 5.5 V 2.4
tBCASTWAIT Broadcast DAC update wait time VIO = 1.7 V to 2.7 V 4 µs
VIO = 2.7 V to 5.5 V 4
SERIAL INTERFACE - READ AND DAISY CHAIN OPERATION, FSDO = 0
f(SCLK) Serial clock frequency VIO = 1.7 V to 2.7 V 15 MHz
VIO = 2.7 V to 5.5 V 20
tSCLKHIGH SCLK high time VIO = 1.7 V to 2.7 V 33 ns
VIO = 2.7 V to 5.5 V 25
tSCLKLOW SCLK low time VIO = 1.7 V to 2.7 V 33 ns
VIO = 2.7 V to 5.5 V 25
tSDIS SDI setup time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tSDIH SDI hold time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tCSS CS to SCLK falling edge setup time VIO = 1.7 V to 2.7 V 30 ns
VIO = 2.7 V to 5.5 V 20
tCSH SCLK falling edge to CS rising edge VIO = 1.7 V to 2.7 V 8 ns
VIO = 2.7 V to 5.5 V 5
tCSHIGH CS high time VIO = 1.7 V to 2.7 V 50 ns
VIO = 2.7 V to 5.5 V 25
tSDOZD SDO tri-state condition to driven VIO = 1.7 V to 2.7 V 0 20 ns
VIO = 2.7 V to 5.5 V 0 20
tSDODLY SDO output delay VIO = 1.7 V to 2.7 V 0 35 ns
VIO = 2.7 V to 5.5 V 0 20
SERIAL INTERFACE - READ AND DAISY CHAIN OPERATION, FSDO = 1
f(SCLK) Serial clock frequency VIO = 1.7 V to 2.7 V 25 MHz
VIO = 2.7 V to 5.5 V 35
tSCLKHIGH SCLK high time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 14
tSCLKLOW SCLK low time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 14
tSDIS SDI setup time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tSDIH SDI hold time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tCSS CS to SCLK falling edge setup time VIO = 1.7 V to 2.7 V 30 ns
VIO = 2.7 V to 5.5 V 20
tCSH SCLK falling edge to CS rising edge VIO = 1.7 V to 2.7 V 8 ns
VIO = 2.7 V to 5.5 V 5
tCSHIGH CS high time VIO = 1.7 V to 2.7 V 50 ns
VIO = 2.7 V to 5.5 V 25
tSDOZD SDO tri-state condition to driven VIO = 1.7 V to 2.7 V 0 20 ns
VIO = 2.7 V to 5.5 V 0 20
tSDODLY SDO output delay VIO = 1.7 V to 2.7 V 0 35 ns
VIO = 2.7 V to 5.5 V 0 20
DIGITAL LOGIC
tLOGDLY CS rising edge to LDAC or CLR falling edge delay time VIO = 1.7 V to 2.7 V 40 ns
tLOGDLY CS rising edge to LDAC or CLR falling edge delay time VIO = 2.7 V to 5.5 V 20
tLDAC LDAC low time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 10
tCLR CLR low time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 10
tRESET POR reset delay VIO = 1.7 V to 2.7 V 1 ms
VIO = 2.7 V to 5.5 V 1
fTOGGLE TOGGLE frequency VIO = 1.7 V to 2.7 V 100 kHz
VIO = 2.7 V to 5.5 V 100