DLPS030E December 2013 – March 2019 DLPC2607
Refer to the PDF data sheet for device specific package drawings
High-speed interface waveform quality and timing on the DLPC2607 ASIC (that is, the mDDR memory I/F and the DMD interface) depend on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.
As an example, the DMD interface system timing margin can be calculated as follows:
The DLPC2607 device I/O timing parameters, as well as mDDR and DMD I/O timing parameters, can be found in their corresponding data sheets. Similarly, PCB routing mismatch can be easily budgeted and met by controlled PCB routing. However, PCB SI degradation is not so straight forward.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines are provided as a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Make sure to confirm any variation from these recommendations with PCB signal integrity analysis or lab measurements.