DLPS030E December   2013  – March 2019 DLPC2607


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Typical Current and Power Dissipation
    6. 6.6  I/O Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  Parallel I/F Frame Timing Requirements
    9. 6.9  Parallel I/F General Timing Requirements
    10. 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
    11. 6.11 BT.656 I/F General Timing Requirements
    12. 6.12 100- to 120-Hz Operational Limitations
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 mDDR Memory Interface Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Parallel Bus Interface
      2. 7.3.2 100- to 120-Hz 3-D Display Operation
    4. 7.4 Programming
      1. 7.4.1 Serial Flash Interface
      2. 7.4.2 Serial Flash Programming
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 System Functional Modes
      2. 8.2.2 Design Requirements
        1. Reference Clock
        2. mDDR DRAM Compatibility
      3. 8.2.3 Detailed Design Procedure
        1. Hot-Plug Usage
        2. Maximum Signal Transition Time
        3. Configuration Control
        4. White Point Correction Light Sensor
      4. 8.2.4 Application Curve
  9. Power Supply Recommendations
    1. 9.1 System Power Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 System Power I/O State Considerations
    4. 9.4 Power-Up Initialization Sequence
    5. 9.5 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  Internal ASIC PLL Power
      2. 10.1.2  General Handling Guidelines for Unused CMOS-Type Pins
      3. 10.1.3  SPI Signal Routing
      4. 10.1.4  mDDR Memory and DMD Interface Considerations
      5. 10.1.5  PCB Design
      6. 10.1.6  General PCB Routing (Applies to All Corresponding PCB Signals)
      7. 10.1.7  Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
      8. 10.1.8  I/F Specific PCB Routing
      9. 10.1.9  Number of Layer Changes
      10. 10.1.10 Stubs
      11. 10.1.11 Termination Requirements:
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. Device Marking
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZVB|176
Thermal pad, mechanical data (Package|Pins)

Power-Up Initialization Sequence

It is assumed that an external power monitor holds the DLPC2607 device in system reset during power-up. It must do this by driving RESET to a logic low state. It should continue to assert system reset until all ASIC voltages have reached minimum specified voltage levels, PARK is asserted high, and input clocks are stable. During this time, most ASIC outputs are driven to an inactive state and all bidirectional signals are configured as inputs to avoid contention. ASIC outputs that are not driven to an inactive state are tri-stated, which includes DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICSZ0. After power is stable and the PLL_REFCLK clock input to the DLPC2607 device is stable, then RESET should be deactivated (set to a logic high). The DLPC2607 device then performs a power-up initialization routine that first locks its PLL, followed by loading self configuration data from the external flash. Upon release of RESET, all DLPC2607 device I/Os become active. Immediately following the release of RESET, the GPIO4_INTF signal is driven high to indicate that the auto-initialization routine is in progress. Upon completion of the auto-initialization routine, the DLPC2607 device drives GPIO4_INTF low to signal INITIALIZATION DONE (also known as INIT DONE).


The host processor can start sending standard I2C commands after GPIO4 (INIT_DONE) goes low, or a 100-ms timer expires in the host processor, whichever is earlier, irrespective of whether the motor is enabled or not. However, before sending any compound I2C commands at power-up, the host processor must wait until GPIO4 (INIT_DONE) goes low, irrespective of whether the motor control function is enabled or not. Due to motor movement, the worst-case time to wait for GPIO4 to go low is when the motor control function is enabled and system dependent; it may take several seconds.

DLPC2607 Initialization_Timeline_dlps30.gifFigure 14. Initialization Timeline