DLPS030E December 2013 – March 2019 DLPC2607
Refer to the PDF data sheet for device specific package drawings
It is assumed that an external power monitor holds the DLPC2607 device in system reset during power-up. It must do this by driving RESET to a logic low state. It should continue to assert system reset until all ASIC voltages have reached minimum specified voltage levels, PARK is asserted high, and input clocks are stable. During this time, most ASIC outputs are driven to an inactive state and all bidirectional signals are configured as inputs to avoid contention. ASIC outputs that are not driven to an inactive state are tri-stated, which includes DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICSZ0. After power is stable and the PLL_REFCLK clock input to the DLPC2607 device is stable, then RESET should be deactivated (set to a logic high). The DLPC2607 device then performs a power-up initialization routine that first locks its PLL, followed by loading self configuration data from the external flash. Upon release of RESET, all DLPC2607 device I/Os become active. Immediately following the release of RESET, the GPIO4_INTF signal is driven high to indicate that the auto-initialization routine is in progress. Upon completion of the auto-initialization routine, the DLPC2607 device drives GPIO4_INTF low to signal INITIALIZATION DONE (also known as INIT DONE).
The host processor can start sending standard I2C commands after GPIO4 (INIT_DONE) goes low, or a 100-ms timer expires in the host processor, whichever is earlier, irrespective of whether the motor is enabled or not. However, before sending any compound I2C commands at power-up, the host processor must wait until GPIO4 (INIT_DONE) goes low, irrespective of whether the motor control function is enabled or not. Due to motor movement, the worst-case time to wait for GPIO4 to go low is when the motor control function is enabled and system dependent; it may take several seconds.