DLPS030E December 2013 – March 2019 DLPC2607
Refer to the PDF data sheet for device specific package drawings
|DMD I/F||Terminate all DMD I/F signals, with the exception of DMD_OEZ (specifically DMD_D(14:0), DMD_DCLK, DMD_TRC, DMD_SCTRL, DMD_LOADB, DMD_DAD_STRB, DMD_DAD_BUS, DMD_SAC_CLK, and DMD_SAC_BUS), at the source with a 10- to 30-Ω series resistor. TI recommends a 30-Ω series resistor for most applications because this minimizes overshoot, undershoot, and reduces EMI; however, for systems that must operate below –20°C, it may be necessary to reduce this series resistance to avoid narrowing the data eye too much under worse-case PVT conditions. TI recommends IBIS simulations for this worse-case scenario.|
|mDDR memory I/F|
|mDDR differential clock||Terminate each line, specifically MEM0_CK(P:N), at the source with a 30-Ω series resistor. Terminate the pair with an external 100-Ω differential termination across the two signals as close to the DRAM as possible. (It may be possible to use a 200-Ω differential termination at the DRAM to save power while still providing sufficient signal integrity, but this has not been validated.)|
|mDDR data, strobe, and mask||Terminate MEM0_DQ(15:0), MEM0_LDM, MEM0_UDM, MEM0_LDQS, and MEM0_UDQS with a 30-Ω series resistor located midway between the two devices.|
|mDDR address and control||Terminate MEM0_A(12:0), MEM0_BA(1:0), MEM0_CKE, MEM0_CSZ, MEM0_RASZ, MEM0_CASZ, and MEM0_WEZ at the source with a 30-Ω series resistor.|
For applications where the routed distance of the mDDR or DMD signal can be maintained to a length of less than 0.75 inches, this signal is short enough not be considered a transmission line and does not need a series terminating resistor.