SPRS956H March 2016 – November 2019 DRA722 , DRA724 , DRA725 , DRA726
Refer to the PDF data sheet for device specific package drawings
The timing parameter values specified in this data manual do not include delays by board routes. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis. If needed, external logic hardware such as buffers may be used to compensate any timing differences.