Product details


Arm CPU 1 ARM Cortex-A15 Arm MHz (Max.) 1500 DSP 1 C66x DSP MHz (Max) 700 Graphics acceleration 1 2D, 1 3D DRAM DDR2-800, DDR3-1333, DDR3L-1333 Co-processor(s) 2 Dual ARM Cortex-M4 Hardware accelerators 1 Image Video Accelerator, 2 Viterbi Decoder, Audio Tracking EMIF 1 32-bit CSI-2 6 DL Other on-chip memory 512 KB Ethernet MAC 10/100/1000, 2-port 1Gb switch Parallel video input ports 4 Display type 1 HDMI OUT, 3 LCD OUT Serial I/O CAN, I2C, SPI, UART, USB Storage interface 1x SDIO 4b, 1x SDIO 8b, 1x UHSI 4b, 1x eMMC 8b PCIe 2 PCIe Gen2 McASP 8 USB 1 USB3.0, 2 USB2.0 open-in-new Find other DRAx digital cockpit SoCs


  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video inputs and video outputs
    • 2D and 3D graphics
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP cores
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • DDR3/DDR3L External Memory Interface (EMIF) module
    • Supports up to DDR3-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Single-core PowerVR™ SGX544 3D GPU
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-Port Gigabit Ethernet switch
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-bit MPU watchdog timer
  • Six high speed Inter-Integrated Circuit (I2C™) ports
  • HDQ/1-Wire® interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad Serial Peripheral Interface (QSPI)
  • Media Local Bus subsystem (MLBSS)
  • Real-Time Clock subsystem (RTCSS)
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High Speed USB 2.0 dual-role device
  • High Speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital®/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® (PCIe®) revision 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B Protocol
  • MIPI® Camera Serial Interface 2 (CSI-2)
  • Up to 215 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and Boot
    • Customer programmable keys (Silicon Revision 2.1)
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)

All trademarks are the property of their respective owners.

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DRA72x ("Jacinto™ 6 Eco") infotainment applications processors are developed on the same architecture as Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family, allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution.

Programmability is provided by a single-core Arm® Cortex®-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm® processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm®, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment is available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet DRA72x Infotainment Applications Processor Silicon Revision 2.0 and 2.1 datasheet (Rev. H) Jul. 24, 2019
* Errata DRA72x and DRA71x SoC for Automotive Infortainment Silicon Errata (Rev. D) Feb. 28, 2017
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC Aug. 24, 2020
White paper Jump Start Upgrading Your Digital Cluster Design with Jacinto 6 Platform (Rev. A) Aug. 17, 2020
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) Jan. 06, 2020
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs Jun. 11, 2019
User guide DRA71x and DRA72x Technical Reference Manual (Rev. D) May 21, 2019
Application note Achieving Early CAN Response on DRA7xx Devices Nov. 28, 2018
Application note DRA74x_75x/DRA72x Performance (Rev. A) Oct. 31, 2018
Application note Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices Sep. 14, 2018
Application note The Implementation of YUV422 Output for SRV Aug. 02, 2018
Application note MMC DLL Tuning (Rev. B) Jul. 31, 2018
Application note Integrating AUTOSAR on TI SoC: Fundamentals Jun. 18, 2018
Application note ECC/EDC on TDAxx (Rev. B) Jun. 13, 2018
Application note Tools and Techniques to Root Case Failures in Video Capture Subsystem Jun. 12, 2018
Application note Sharing VPE Between VISIONSDK and PSDKLA May 04, 2018
Technical articles Smart sensors are going to change how you drive (because eventually, you won’t) Apr. 25, 2018
Application note Android Boot Optimization on DRA7xx Devices (Rev. A) Feb. 13, 2018
Technical articles AI in Automotive: Practical deep learning Feb. 08, 2018
Technical articles How to maintain automotive front camera thermal performance on a hot summer day Feb. 02, 2018
Technical articles Development platforms pave the way to production systems for ADAS Jan. 19, 2018
Application note Flashing Utility - mflash Jan. 09, 2018
Application note Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) Nov. 30, 2017
Application note Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) Nov. 27, 2017
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) Nov. 07, 2017
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) Nov. 03, 2017
Application note Robust Rear-View Camera (RVC) App Report Sep. 13, 2017
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC Sep. 12, 2017
Application note Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices Aug. 14, 2017
Application note Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices Jul. 12, 2017
White paper Revolutionize the automotive cockpit Jun. 02, 2017
Application note Linux Boot Time Optimizations on DRA7xx Devices Mar. 31, 2017
Application note Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) Feb. 17, 2017
Application note Early Splash Screen on DRA7x Devices Jan. 31, 2017
User guide DM369 Camera Starter Kit (CSK) User's Guide Dec. 15, 2016
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) Dec. 15, 2016
User guide DRA72x EVM CPU Board User's Guide Dec. 07, 2016
Application note Gstreamer Migration Guidelines Apr. 26, 2016
User guide Jacinto6 Android Video Decoder Software Design Specification User's Guide Apr. 21, 2016
User guide Jacinto6 Android Video Encoder Software Design Specification User's Guide Apr. 21, 2016
Application note Flashing Binaries to DRA7xx Factory Boards Using DFU Apr. 14, 2016
Application note Tools and Techniques for Audio Debugging Apr. 13, 2016
Application note Debugging Tools and Techniques With IPC3.x Mar. 30, 2016
Application note Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) Jan. 15, 2016
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device Aug. 13, 2014
White paper Today’s high-end infotainment soon becoming mainstream Jun. 02, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development


Jacinto™ DRA72x Evaluation Module (EVM) is an evaluation platform designed to speed up development efforts and reduce time to market for applications such as infotainment, reconfigurable digital cluster or integrated digital cockpit. To allow scalability and re-use across Jacinto (...)



  • DRA72x Processor
  • 2GB DDR3L
  • TPS65917 Power Management IC
  • 4 GB eMMC
  • 10.1" 1920X1200 Capacitive Touch Screen LCD option
  • JAMR3 tuner board


  • Linux
  • Android
  • StarterWare


  • Gigabit Ethernet (2)
  • PCIe
  • e/mSATA
  • Micro SD Card
  • Micro USB 2.0
  • USB 3.0
  • HDMI
  • Audio in/out
  • WiLink8 Q (Connector

The Texas Instruments XDS110 is a new class of debug probe (emulator) for TI embedded processors. The XDS110 replaces the XDS100 family while supporting a wider variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. Also, all XDS debug probes support Core and System Trace in all ARM and (...)


The XDS110 is the latest entry level debug probe (emulators) for TI embedded processors. Designed to be a complete solution that delivers JTAG and SWD connectivity at a low cost, the XDS110 is the debug probe of choice for entry-level debugging of TI microcontrollers, processors and SimpleLink (...)

Software development

Processor Software Development Kit for DRA7x Jacinto™ Processors – Linux, Android, and RTOS
PROCESSOR-SDK-DRA7X Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

Processor SDK Linux Automotive features
  • Open Linux support
  • Linux kernel and Bootloaders
  • File system
  • Qt/Webkit application framework
  • 3D graphics support
  • 2D graphics support
  • Integrated WLAN and Bluetooth® support
  • GUI-based application launcher
  • Example applications, including:
    • ARM benchmarks: Dhrystone, Linpack (...)

Design tools & simulation

SPRM681.ZIP (1 KB) - Thermal Model
SPRM683.ZIP (12619 KB) - IBIS Model
SPRM684.ZIP (13 KB) - BSDL Model
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors
CLOCKTREETOOL The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree elements (...)

CAD/CAE symbols

Package Pins Download
FCBGA (ABC) 760 View options

Ordering & quality

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Support & training

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