SPRS950F December 2015 – May 2019 DRA744 , DRA745 , DRA746 , DRA750 , DRA756
Refer to the PDF data sheet for device specific package drawings
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need for a complex timing closure process. For more information regarding the guidelines for using this DDR2 specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification.