Dual 1.5 GHz A15, dual EVE, dual DSP, extended peripherals SoC processor for infotainment
Product details
Parameters
Features
- Architecture designed for infotainment applications
- Video, image, and graphics processing support
- Full-HD video (1920 × 1080p, 60 fps)
- Multiple video input and video output
- 2D and 3D graphics
- Dual Arm® Cortex®-A15 microprocessor subsystem
- Up to two C66x floating-point VLIW DSP
- Fully object-code compatible with C67x and C64x+
- Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle
- Up to 2.5MB of on-chip L3 RAM
- Level 3 (L3) and level 4 (L4) interconnects
- Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
- Supports up to DDR2-800 and DDR3-1066
- Up to 2GB supported per EMIF
- Dual Arm® Cortex®-M4 Image Processing Units (IPU)
- Up to two Embedded Vision Engines (EVEs)
- IVA subsystem
- Display subsystem
- Display controller with DMA engine and up to three pipelines
- HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
- Video Processing Engine (VPE)
- 2D-graphics accelerator (BB2D) subsystem
- Vivante® GC320 core
- Dual-core PowerVR® SGX544 3D GPU
- Three Video Input Port (VIP) modules
- Support for up to 10 multiplexed input ports
- General-Purpose Memory Controller (GPMC)
- Enhanced Direct Memory Access (EDMA) controller
- 2-port gigabit ethernet (GMAC)
- Sixteen 32-Bit general-purpose timers
- 32-Bit MPU watchdog timer
- Five Inter-Integrated Circuit (I2C™) ports
- HDQ™/1-Wire® interface
- SATA interface
- MediaLB® (MLB) subsystem
- Ten configurable UART/IrDA/CIR modules
- Four Multichannel Serial Peripheral Interfaces (McSPI)
- Quad SPI (QSPI)
- Eight Multichannel Audio Serial Port (McASP) modules
- SuperSpeed USB 3.0 dual-role device
- Three high-speed USB 2.0 dual-role devices
- Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
- PCI-Express® 3.0 subsystems with two 5-Gbps lanes
- One 2-lane gen2-compliant port
- or Two 1-lane gen2-compliant ports
- Dual Controller Area Network (DCAN) modules
- CAN 2.0B protocol
- Up to 247 General-Purpose I/O (GPIO) pins
- Real-Time Clock SubSystem (RTCSS)
- Device security features
- Hardware crypto accelerators and DMA
- Firewalls
- JTAG® lock
- Secure keys
- Secure ROM and boot
- Power, Reset, and Clock Management (PRCM)
- On-chip debug with CTools technology
- 28-nm CMOS technology
- 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)
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Description
DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.
The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.
Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.
The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The Jacinto™ DRA7xx evaluation module platform designed to speed up development efforts and reduce time to market for applications such as infotainment, reconfigurable digital cluster or integrated digital cockpit. To allow scalability and re-use across DRA74x and DRA75x Jacinto (...)
Features
- Hardware
- DRA75x processor
- 4GB DDR3L
- TPS659039 power management IC
- 4 GB eMMC
- 10.1" 1920X1200 capacitive touch screen LCD option
- JAMR3 tuner board
- Software
- Linux®
- Android™
- StarterWare
- Connectivity
- Gigabit Ethernet (2)
- MiniPCIe
- e/mSATA
- Micro SD card
- Micro USB 2.0
- USB 3.0
- HDMI
- Audio in/out
- WiLink™ 8Q connector
Description
The DRA77xP/DRA76xP-ACD is an evaluation platform designed to allow scalability and re-use across DRA77xP and DRA76xP JacintoTM Infotainment System-on-Chips (SoCs), it is based on Jacinto DRA77xP SoC that incorporates a heterogeneous, scalable architecture that includes a mix of two ARM Cortex-A15 (...)
Features
- Hardware
- DRA77xP Processor
- 4GB DDR3L
- TPS65917 + LP87565 Power Management IC Devices
- 4GB eMMC
- Software
- PROCESSOR-SDK-DRA7X
- Connectivity
- Gigabit Ethernet (2)
- MiniPCIe
- e/mSATA
- Micro SD Card
- Micro USB 2.0
- USB 3.0
- HDMI
- Audio in/out
- WiLink8 Q (Connector)
Software development
Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)
Features
- Open Linux support
- Linux kernel and Bootloaders
- File system
- Qt/Webkit application framework
- 3D graphics support
- 2D graphics support
- Integrated WLAN and Bluetooth® support
- GUI-based application launcher
- Example applications, including:
- ARM benchmarks: Dhrystone, Linpack (...)
Design tools & simulation
- Visualize the device clock tree
- Interact with clock tree elements (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
FCBGA (ABC) | 760 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
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