Top

Product details

Parameters

Arm CPU 2 ARM Cortex-A15 Arm MHz (Max.) 1000 DSP 2 C66x DSP MHz (Max) 750 Graphics acceleration 1 2D, 2 3D DRAM DDR2-800, DDR3-1066, DDR3L-1066 Co-processor(s) 2 Dual ARM Cortex-M4 Hardware accelerators 1 Image Video Accelerator, 2 Viterbi Decoder, Audio Tracking EMIF 2 32-bit Other on-chip memory 512 KB Ethernet MAC 10/100/1000, 2-port 1Gb switch Parallel video input ports 10 Display type 1 HDMI OUT, 3 LCD OUT Serial I/O CAN, I2C, SPI, UART, USB Storage interface 1x SDIO 4b, 1x SDIO 8b, 1x UHSI 4b, 1x eMMC 8b PCIe 2 PCIe Gen2 McASP 8 USB 1 USB3.0, 3 USB2.0 open-in-new Find other DRAx digital cockpit SoCs

Features

  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Up to two Embedded Vision Engines (EVEs)
  • IVA subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
  • Sixteen 32-Bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Five Inter-Integrated Circuit (I2C™) ports
  • HDQ™/1-Wire® interface
  • SATA interface
  • MediaLB® (MLB) subsystem
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRCM)
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)

All trademarks are the property of their respective owners.

open-in-new Find other DRAx digital cockpit SoCs

Description

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.

open-in-new Find other DRAx digital cockpit SoCs
Download

More Information

For more information on the DRA750  Request Now

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 46
Type Title Date
* Datasheet DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0 datasheet (Rev. F) May 07, 2019
* Errata DRA75x, DRA74x Silicon Errata Automotive Infotainment Silicon Revision 2.0, 1.1 (Rev. I) Sep. 20, 2017
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC Aug. 24, 2020
User guide DRA75x, DRA74x Technical Reference Manual (SR2.0 & SR1.1) (Rev. G) Feb. 21, 2020
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) Jan. 06, 2020
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs Jun. 11, 2019
Application note Achieving Early CAN Response on DRA7xx Devices Nov. 28, 2018
Application note DRA74x_75x/DRA72x Performance (Rev. A) Oct. 31, 2018
Application note Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices Sep. 14, 2018
Application note The Implementation of YUV422 Output for SRV Aug. 02, 2018
Application note MMC DLL Tuning (Rev. B) Jul. 31, 2018
Application note Integrating AUTOSAR on TI SoC: Fundamentals Jun. 18, 2018
Application note ECC/EDC on TDAxx (Rev. B) Jun. 13, 2018
Application note Tools and Techniques to Root Case Failures in Video Capture Subsystem Jun. 12, 2018
Application note Sharing VPE Between VISIONSDK and PSDKLA May 04, 2018
Technical articles Smart sensors are going to change how you drive (because eventually, you won’t) Apr. 25, 2018
Application note Android Boot Optimization on DRA7xx Devices (Rev. A) Feb. 13, 2018
Technical articles AI in Automotive: Practical deep learning Feb. 08, 2018
Technical articles How to maintain automotive front camera thermal performance on a hot summer day Feb. 02, 2018
Technical articles Development platforms pave the way to production systems for ADAS Jan. 19, 2018
Application note Flashing Utility - mflash Jan. 09, 2018
Application note Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) Nov. 30, 2017
Application note Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) Nov. 27, 2017
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) Nov. 07, 2017
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) Nov. 03, 2017
Application note Robust Rear-View Camera (RVC) App Report Sep. 13, 2017
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC Sep. 12, 2017
Application note Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices Aug. 14, 2017
Application note Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices Jul. 12, 2017
White paper Revolutionize the automotive cockpit Jun. 02, 2017
Application note Linux Boot Time Optimizations on DRA7xx Devices Mar. 31, 2017
Application note Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) Feb. 17, 2017
Application note Early Splash Screen on DRA7x Devices Jan. 31, 2017
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) Dec. 15, 2016
Application note Gstreamer Migration Guidelines Apr. 26, 2016
User guide Jacinto6 Android Video Decoder Software Design Specification User's Guide Apr. 21, 2016
User guide Jacinto6 Android Video Encoder Software Design Specification User's Guide Apr. 21, 2016
Application note Flashing Binaries to DRA7xx Factory Boards Using DFU Apr. 14, 2016
Application note Tools and Techniques for Audio Debugging Apr. 13, 2016
Application note Debugging Tools and Techniques With IPC3.x Mar. 30, 2016
User guide DRA75x and DRA74x EVM CPU Board User's Guide Feb. 09, 2016
User guide JAMR3 Tuner Application Board User’s Guide Feb. 09, 2016
Application note Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) Jan. 15, 2016
White paper Informational ADAS as Software Upgrade to Today’s Infotainment Systems Oct. 14, 2014
More literature DRA75x “Jacinto 6 EP” and “Jacinto 6 Ex” Automotive Product Bulletin Sep. 25, 2014
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device Aug. 13, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
DRA7xx Evaluation Module
Provided by Spectrum Digital Inc.
Description

The Jacinto™ DRA7xx evaluation module platform designed to speed up development efforts and reduce time to market for applications such as infotainment, reconfigurable digital cluster or integrated digital cockpit. To allow scalability and re-use across DRA74x and DRA75x Jacinto (...)

Features
  • Hardware
    • DRA75x processor
    • 4GB DDR3L
    • TPS659039 power management IC
    • 4 GB eMMC
    • 10.1" 1920X1200 capacitive touch screen LCD option
    • JAMR3 tuner board
  • Software
    • Linux®
    • Android™
    • StarterWare
  • Connectivity
    • Gigabit Ethernet (2)
    • MiniPCIe
    • e/mSATA
    • Micro SD card
    • Micro USB 2.0
    • USB 3.0
    • HDMI
    • Audio in/out
    • WiLink™ 8Q  connector
EVALUATION BOARD Download
DRA7xP Evaluation Module
Provided by Spectrum Digital Inc.
Description

The DRA77xP/DRA76xP-ACD is an evaluation platform designed to allow scalability and re-use across DRA77xP and DRA76xP JacintoTM Infotainment System-on-Chips (SoCs), it is based on Jacinto DRA77xP SoC that incorporates a heterogeneous, scalable architecture that includes a mix of two ARM Cortex-A15 (...)

Features
  • Hardware
    • DRA77xP Processor
    • 4GB DDR3L
    • TPS65917 + LP87565 Power Management IC Devices
    • 4GB eMMC
  • Software
    • PROCESSOR-SDK-DRA7X
  • Connectivity
    • Gigabit Ethernet (2)
    • MiniPCIe
    • e/mSATA
    • Micro SD Card
    • Micro USB 2.0
    • USB 3.0
    • HDMI
    • Audio in/out
    • WiLink8 Q (Connector)
DEBUG PROBE Download
99
Description

The Texas Instruments XDS110 is a new class of debug probe (emulator) for TI embedded processors. The XDS110 replaces the XDS100 family while supporting a wider variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. Also, all XDS debug probes support Core and System Trace in all ARM and (...)

Features

The XDS110 is the latest entry level debug probe (emulators) for TI embedded processors. Designed to be a complete solution that delivers JTAG and SWD connectivity at a low cost, the XDS110 is the debug probe of choice for entry-level debugging of TI microcontrollers, processors and SimpleLink (...)

Software development

SOFTWARE DEVELOPMENT KIT (SDK) Download
Processor Software Development Kit for DRA7x Jacinto™ Processors – Linux, Android, and RTOS
PROCESSOR-SDK-DRA7X Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

Features
Processor SDK Linux Automotive features
  • Open Linux support
  • Linux kernel and Bootloaders
  • File system
  • Qt/Webkit application framework
  • 3D graphics support
  • 2D graphics support
  • Integrated WLAN and Bluetooth® support
  • GUI-based application launcher
  • Example applications, including:
    • ARM benchmarks: Dhrystone, Linpack (...)

Design tools & simulation

SIMULATION MODEL Download
SPRM667.ZIP (14 KB) - BSDL Model
SIMULATION MODEL Download
SPRM668.ZIP (18366 KB) - IBIS Model
SIMULATION MODEL Download
SPRM669.ZIP (2 KB) - Thermal Model
CALCULATION TOOL Download
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors
CLOCKTREETOOL The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree elements (...)

CAD/CAE symbols

Package Pins Download
FCBGA (ABC) 760 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos