Refer to the PDF data sheet for device specific package drawings
The TMDS signals are high speed differential pairs. Care must be taken in the PCB layout of these signals to ensure good signal integrity.
The TMDS differential signal traces must be routed to achieve 100 Ω (+/- 10%) differential impedance and 60 Ω (+/-10%) single ended impedance. Single ended impedance control is required because differential signals can’t be closely coupled on PCBs and therefore single ended impedance becomes important.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as close to 60 Ω impedance traces as possible. For best accuracy, work with your PCB fabricator to ensure this impedance is met.
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing variations affect impedance dramatically, so tight impedance control can be more problematic to maintain in production.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing make obstacle avoidance easier, and trace width variations don’t affect impedance as much, therefore it’s easier to maintain accurate impedance over the length of the signal. The wider traces also show reduced skin effect and therefore often result in better signal integrity.
Some general routing guidelines regarding TMDS:
Table 7-14 shows the routing specifications for the TMDS signals.
|Device balls to HDMI header trace length||4000||Mils|
|Skew within a differential pair||3||5||Mils|
|Number of stubs allowed on TMDS traces||0||stubs|
|TMDS pair differential impedance||90||100||110||Ω|
|TMDS single-ended impedance||54||60||66||Ω|
|Number of vias on each TMDS trace||0||Vias|
|TMDS differential pair to any other trace spacing (1)(2)(3)||2×DS||3xDS||Mils|
|Number of ground plane cuts allowed within HDMI routing region (except for specific ground carving as explained in this document)||0||Cuts|
|Number of layers between HDMI routing region and reference ground plane||0||Layers|
|PCB trace width||4.4||Mils|
|ESD part number||TPD1E05U06||Minimize capacitance (0.42pF)|
|Carve Ground||Carve GND underneath ESD and CMF||Minimize capacitance under ESD and CMF|
|Round pads||Reduce pad size and round the corners of the pads for the ESD and CMF components||Minimize capacitance|
|Routing layer||Route all signals only on the same layer as SoC||Minimize reflection loss|
Figure 7-44presents an example layout, demonstrating the “carve GND” concept.