SBOSAA4B April   2025  – August 2025 INA1H94-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: INA1H94-SP
    5. 5.5 Electrical Characteristics: VS = ±9V
    6. 5.6 Electrical Characteristics: V+ = 5V and V– = 0V
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Common-Mode Range
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 SAR ADC 12-B, 8-Channel Battery Cell Voltage Monitor
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.1.2 Detailed Design Procedure

  1. Select high-grade C0G (NP0) capacitor for CFIL to improve linearity and reduce settling errors.
  2. On the battery monitor circuit using bipolar supply, connect the REFA and REFB input reference pins to GND using short, low impedance connections.
  3. On the battery monitor circuit using unipolar supply, use a precision, low-noise, low output impedance reference circuits to drive REFA and REFB inputs.
  4. Use precision 0.05%, low drift resistors for RDIV1 and RDIV2 to minimize error and drift on the voltage divider. The resistor values are scaled for a 4.2V battery cell and a 5V full-scale range ADC.
  5. The R-C filter placed at the ADC128S102-SP input drives the SAR as a charge kickback filter. The filter component values depend on the data converter sampling rate, the ADC sample-and-hold structure, and the data converter requirements. The filter combination (RFIL and CFIL) is tuned for ADC sample-and-hold settling performance while maintaining amplifier stability. The component value selection is dependent on the data converter sampling rate, the ADC sample-and-hold structure.
  6. The R-C filter values shown in this example provide good stability and settling performance for the LMP7704-SP driving the ADC128S102-SP 12-bit, SAR ADC at 500kSPS sampling rate. If the circuit is modified, or a higher sampling rate is required, the circuit designer can select a different buffer amplifier and R-C filter values depending on the ADC characteristics, and application needs.