SWRS211C May 2017 – October 2018 IWR1443
As soon as device reset is de-asserted, the R4F processor of the Master (Control) system starts executing its bootloader from an on-chip ROM memory.
The bootloader of the Master system operates in two basic modes and these are specified on the user hardware (Printed Circuit Board) by configuring what are termed as “Sense on Power” (SOP) pins. These pins on the device boundary are scanned by the bootloader firmware and choice of mode for bootloader operation is made.
Table 6-4 enumerates the relevant SOP combinations and how these map to bootloader operation.
|SOP2 (P13)||SOP1 (P11)||SOP0 (J13)||BOOTLOADER MODE AND OPERATION|
Device Bootloader loads user application from QSPI Serial Flash to internal RAM and switches the control to it
Device Bootloader spins in loop to allow flashing of user application (or device firmware patch – Supplied by TI) to the serial flash
Bootloader is bypassed and R4F processor is halted. This allows user to connect emulator at a known point