SWRS211C May 2017 – October 2018 IWR1443
An external crystal is connected to the device pins. Figure 5-4 shows the crystal implementation.
The load capacitors, Cf1 and Cf2 in Figure 5-4, should be chosen such that Equation 1 is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator CLKP and CLKM pins.Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.
Table 5-6 lists the electrical characteristics of the clock crystal.
|fP||Parallel resonance crystal frequency||40||MHz|
|CL||Crystal load capacitance||5||8||12||pF|
|Temperature range||Expected temperature range of operation||–40||105||ºC|
|Frequency tolerance||Crystal frequency tolerance(1)(2)(3)||–50||50||ppm|
In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 5-7 lists the electrical characteristics of the external clock signal.
External AC-coupled sine wave or DC-coupled square wave
Phase Noise referred to 40 MHz
|Phase Noise at 1 kHz||–132||dBc/Hz|
|Phase Noise at 10 kHz||–143||dBc/Hz|
|Phase Noise at 100 kHz||–152||dBc/Hz|
|Phase Noise at 1 MHz||–153||dBc/Hz|