SWRS211C May 2017 – October 2018 IWR1443
The Radio Processor subsystem (also referred to as BIST Subsystem in this document) includes the digital front-end, the ramp generator and an internal processor for control / configuration of the low-level RF/analog and ramp generator registers. The Radar Processor also schedules periodic monitoring tasks. User applications, running on
Master (Control) System, do not have direct access to Radar System; access is based on well-defined API messages (over a hardware channel) from the master subsystem.
This radio processor is programmed by TI and takes care of RF calibration and self-test/monitoring functions (BIST). This processor is not available directly for customer use/application.
The digital front-end takes care of filtering and decimating the raw sigma-delta ADC output and provides the final ADC data samples at a programmable sampling rate.