SNVSAA7B December   2015  – July 2021 LM53625-Q1 , LM53635-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Input Voltage Frequency Foldback
    5. 8.5 Spread-Spectrum Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. External Components Selection
            1. Input Capacitors
              1. Input Capacitor Selection
            2. Output Inductors and Capacitors Selection
              1. Inductor Selection
              2. Output Capacitor Selection
          2. Setting the Output Voltage
            1. FB for Adjustable Versions
          3. VCC
          4. BIAS
          5. CBOOT
          6. Maximum Ambient Temperature
        3. Application Curves
      2. 9.2.2 Fixed 5-V Output for USB-Type Applications
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 9.2.3 Fixed 3.3-V Output
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      4. 9.2.4 Adjustable Output
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNL|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

RESET Flag Output

The RESET function, built into the LM53625/35-Q1, has special features not found in the ordinary Power-Good function. A glitch filter prevents false flag operation for short excursions in the output voltage, such as during line and load transients. Furthermore, there is a delay between the point at which the output voltage is within specified limits and the flag asserts Power Good. Because the RESET comparator and the regulation loop share the same reference, the thresholds track with the output voltage. This allows the LM53625/35-Q1 to be specified with a 96.5% maximum threshold, while at the same time specifying a 94 % worst case threshold with respect to the actual output voltage for that device. This allows tighter tolerance than is possible with an external supervisor device. The net result is a more accurate Power-Good function while expanding the system allowance for transients, and so forth. RESET operation can best be understood by reference to Figure 8-2 and Figure 8-3. The values for the various filter and delay times can be found in Section 7.7. Output voltage excursions lasting less than TRESET-filter do not trip RESET. Once the output voltage is within the prescribed limits, a delay of TRESET-act is imposed before RESET goes high.

This output consists of an open-drain NMOS; requiring an external pullup resistor to a suitable logic supply. It can also be pulled up to either VCC or VOUT, through an appropriate resistor, as desired. The pin can be left floating or grounded if the RESET function is not used in the application. When EN is pulled low, the flag output isl also be forced low. With EN low, RESET remains valid as long as the input voltage is ≥ 1.5 V. The maximum current into this pin should be limited to 10 mA, while the maximum voltage must be less than 8 V.

GUID-71392FC9-B6D5-4129-82F7-162A1C5CD84C-low.png Figure 8-2 Static RESET Operation
GUID-CA1734B7-C391-40B4-8CC5-B03ADCB38175-low.png Figure 8-3 RESET Timing Behavior

While the LM53625/35-Q1 reset function resembles a standard Power-Good function, its functionality is designed to replace a discrete reset device, reducing additional component cost. There are three major differences between the reset function and the normal power good function seen in most regulators.

  • RESET Output signals a fault (pulls its output to ground) while the part is disabled.
  • RESET Continues to operate with input voltage as low as 1.5 V. Below this input voltage, RESET Output may be high impedance.

The threshold voltage for the RESET function is specified taking advantage of the availability of the LM53625/35-Q1 internal feedback threshold to the RESET circuit. This allows a maximum threshold of 96.5% of selected output voltage to be specified at the same time as 96 % of actual set point. The net result is a more accurate reset function while expanding the system allowance for transient response without the need for extremely accurate internal circuitry.