It is often desirable to synchronize the operation of multiple regulators in a single system. This technique results in better-defined EMI and can reduce the need for capacitance on some power rails. The LM53625/35-Q1 provides a SYNC input which allows synchronization with an external clock. The LM53625/35-Q1 implements an in-phase locking scheme – the rising edge of the clock signal provided to the LM53625/35-Q1 input corresponds to turning on the high-side device within the LM53625/35-Q1. This function is implemented using phase locking over a limited frequency range eliminating large glitches upon initial application of an external clock. The clock fed into the LM53625/35-Q1 replaces the internal free running clock but does not affect frequency foldback operation. Output voltage continues to be well regulated with duty factors outside of the normal 15% through 87% range though at reduced frequency.
The internal clock of the LM53625/35-Q1 can be synchronized to a system clock through the SYNC input. This input recognizes a valid high level as that ≥ 1.5 V, and a valid low as that ≤ 0.4 V. The frequency synchronization signal must be in the range of 1.9 MHz to 2.3 MHz with a duty cycle of from 10% to 90%. The internal clock is synced to the rising edge of the external clock. Ground this input if not used. The maximum voltage on this input is 5.5 V and should not be allowed to float. See Section 8.4 to determine which modes are valid for synchronizing the clock.
The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided.