SNOSDE8A July   2023  – September 2023 LM74912-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump
      2. 8.3.2 Dual Gate Control (DGATE, HGATE)
        1. 8.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 8.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 8.3.3 Short Circuit Protection (CS+, CS-, ISCP)
      4. 8.3.4 Overvoltage Protection and Battery Voltage Sensing (SW, OV, UVLO)
      5. 8.3.5 Low IQ SLEEP Mode (SLEEP, SLEEP_OV)
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Automotive Reverse Battery Protection
        1. 9.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
        2. 9.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
        3. 9.2.2.3 Input Micro-Short Protection: LV124 E-10
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Design Considerations
        2. 9.2.3.2 Charge Pump Capacitance VCAP
        3. 9.2.3.3 Input , Supply and Output Capacitance
        4. 9.2.3.4 Hold-Up Capacitance
        5. 9.2.3.5 Overvoltage Protection and Battery Monitor
        6. 9.2.3.6 Selecting Short Circuit Current Threshold
          1. 9.2.3.6.1 Selection of Scaling Resistor RSET and RISCP for Short Circuit Protection
      4. 9.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 9.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 9.2.6 TVS Selection
      7. 9.2.7 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 TVS Selection for 12-V Battery Systems
      3. 9.4.3 TVS Selection for 24-V Battery Systems
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2.1 Reverse Battery Protection (A, C, DGATE)

A, C, DGATE comprises the ideal diode stage. Connect the source of the external MOSFET to A, drain to C, and gate to DGATE. The LM74912-Q1 has integrated reverse input protection down to –65 V.

Before the DGATE driver is enabled, the following conditions must be achieved:

  • The EN and SLEEP pin voltage must be greater than the specified input high voltage.
  • The CAP to VS voltage must be greater than the undervoltage lockout voltage.
  • Voltage at A pin must be greater than VA POR rising threshold.
  • Voltage at VS pin must be greater than VS POR rising threshold.
If the above conditions are not achieved, then the DGATE pin is internally connected to the A pin, assuring that the external MOSFET is disabled.

In LM74912-Q1 the voltage drop across the MOSFET is continuously monitored between the A and C pins, and the DGATE to A voltage is adjusted as needed to regulate the forward voltage drop at 10.5 mV (typ). This closed loop regulation scheme enables graceful turn off of the MOSFET during a reverse current event and ensures zero DC reverse current flow. This scheme ensures robust performance during slow input voltage ramp down tests. Along with the linear regulation amplifier scheme, the LM74912-Q1 also integrates a fast reverse voltage comparator. When the voltage drop across A and C reaches V(AC_REV) threshold then the DGATE goes low within 0.5 µs (typ). This fast reverse voltage comparator scheme ensures robust performance during fast input voltage ramp down tests such as input micro-shorts. The external MOSFET is turned ON back when the voltage across A and C hits V(AC_FWD) threshold within 0.8 µs (typ).