SNOSDE8A July   2023  – September 2023 LM74912-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump
      2. 8.3.2 Dual Gate Control (DGATE, HGATE)
        1. 8.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 8.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 8.3.3 Short Circuit Protection (CS+, CS-, ISCP)
      4. 8.3.4 Overvoltage Protection and Battery Voltage Sensing (SW, OV, UVLO)
      5. 8.3.5 Low IQ SLEEP Mode (SLEEP, SLEEP_OV)
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Automotive Reverse Battery Protection
        1. 9.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
        2. 9.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
        3. 9.2.2.3 Input Micro-Short Protection: LV124 E-10
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Design Considerations
        2. 9.2.3.2 Charge Pump Capacitance VCAP
        3. 9.2.3.3 Input , Supply and Output Capacitance
        4. 9.2.3.4 Hold-Up Capacitance
        5. 9.2.3.5 Overvoltage Protection and Battery Monitor
        6. 9.2.3.6 Selecting Short Circuit Current Threshold
          1. 9.2.3.6.1 Selection of Scaling Resistor RSET and RISCP for Short Circuit Protection
      4. 9.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 9.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 9.2.6 TVS Selection
      7. 9.2.7 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 TVS Selection for 12-V Battery Systems
      3. 9.4.3 TVS Selection for 24-V Battery Systems
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) =  V(OUT) = V(VS) = 12 V,  C(CAP) = 0.1 µF, V(EN) , V(SLEEP)= 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDGATE_OFF(dly) DGATE turn off delay during reverse voltage detection V(A) – V(C) = +30 mV to –100 mV to V(DGATE–A) < 1 V, C(DGATE–A) = 10 nF 0.5 0.95 µs
tDGATE_ON(dly) DGATE turn on delay during forward voltage detection V(A) – V(C) = –20 mV to +700 mV to V(DGATE–A) > 5 V, C(DGATE–A) = 10 nF 0.8 1.6 µs
tEN(dly)_DGATE DGATE turn on delay during device enable EN↑ to V(DGATE–A) > 5 V 185 270 µs
tUVLO_OFF(deg)_HGATE HGATE turn off de-glitch during UVLO UVLO↓ to HGATE ↓  5 7 µs
tUVLO_ON(deg)_HGATE HGATE turn on de-glitch during UVLO UVLO ↑ to HGATE ↑ 7 µs
tOVP_OFF(deg)_HGATE HGATE turn off de-glitch during OV OV ↑ to HGATE ↓, C(HGATE–OUT) = 4.7 nF 4 7 µs
tOVP_ON(deg)_HGATE HGATE turn on de-glitch during OV OV ↓ to HGATE ↑ 7 µs
tSCP_DLY Short-circuit protection turn off delay (VCS+–VISCP) = 0-mV to 100-mV, HGATE↓, C(HGATE–OUT) = 10 nF
 		 2 4.5 µs
tFLT_ASSERT Fault assert delay during short-circuit condition (VCS+–VISCP)↑ to FLT↓
 		 2.5 µs
tFLT_DE-ASSERT Fault de-assert delay (VCS+–VISCP) ↓ to FLT↑ 3.5 µs
tSLEEP_OCP_LATCH SLEEP OCP Latch delay SLEEP = Low, EN = High 3.5 7.5 µs
tSLEEP_OV_OFF Overvoltage turn off response delay in sleep mode  SLEEP = Low, EN = High 3.5 µs
tSLEEP_MODE_ENTRY Sleep Mode Entry Delay SLEEP = Low, EN = High 100 µs