SNOSDE8A July   2023  – September 2023 LM74912-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump
      2. 8.3.2 Dual Gate Control (DGATE, HGATE)
        1. 8.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 8.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 8.3.3 Short Circuit Protection (CS+, CS-, ISCP)
      4. 8.3.4 Overvoltage Protection and Battery Voltage Sensing (SW, OV, UVLO)
      5. 8.3.5 Low IQ SLEEP Mode (SLEEP, SLEEP_OV)
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Automotive Reverse Battery Protection
        1. 9.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
        2. 9.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
        3. 9.2.2.3 Input Micro-Short Protection: LV124 E-10
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Design Considerations
        2. 9.2.3.2 Charge Pump Capacitance VCAP
        3. 9.2.3.3 Input , Supply and Output Capacitance
        4. 9.2.3.4 Hold-Up Capacitance
        5. 9.2.3.5 Overvoltage Protection and Battery Monitor
        6. 9.2.3.6 Selecting Short Circuit Current Threshold
          1. 9.2.3.6.1 Selection of Scaling Resistor RSET and RISCP for Short Circuit Protection
      4. 9.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 9.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 9.2.6 TVS Selection
      7. 9.2.7 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 TVS Selection for 12-V Battery Systems
      3. 9.4.3 TVS Selection for 24-V Battery Systems
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20220418-SS0I-TRBW-DDVW-HR0CSFDS8JV7-low.svgFigure 5-1 RGE Package,24-Pin VQFN(Transparent Top View)
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
DGATE1ODiode controller gate drive output. Connect to the GATE of the external MOSFET.
A2IAnode of the ideal diode. Connect to the source of the external MOSFET.
SW3IVoltage sensing disconnect switch terminal. A and SW are internally connected through a switch. Use SW as the top connection of the battery sensing or OV resistor ladder network. When EN/SLEEP is pulled low, the switch is OFF disconnecting the resistor ladder from the battery line thereby cutting off the leakage current. If the internal disconnect switch between A and SW is not used then SW pin can be left floating or pulled to A.
UVLO4IAdjustable undervoltage threshold input. Connect a resistor ladder across SW to UVLO terminal to GND. When the voltage at UVLO goes below the undervoltage cut-off threshold then the HGATE is pulled low turning OFF the HSFET. HGATE turns ON when the sense voltage goes above the UVLO falling threshold.
OV5IAdjustable overvoltage threshold input. Connect a resistor ladder across SW to OV terminal. When the voltage at OV exceeds the overvoltage cut-off threshold then the HGATE is pulled low turning OFF the HSFET. HGATE turns ON when the sense voltage goes below the OV falling threshold.
EN6IEN input. Connect to VS pin for always ON operation. Can be driven externally from a micro controller I/O. Pulling it low below V(ENF) makes the device enter into low Iq shutdown mode.
SLEEP7IActive low SLEEP mode input. Can be driven from the micro-controller. When pulled low device enters into low power state with charge pump and gate drive turned off. Internal bypass switch provides output voltage with limited current capacity. When not used, should be tied to EN or VS.
N.C.8—No connection. Keep this pin floating.
N.C.9—No connection. Keep this pin floating.
N.C.10—No connection. Keep this pin floating.
N.C.11—No connection. Keep this pin floating.
FLT12OOpen drain fault output. FLT pin is pulled low in case of undervoltage, overvoltage or output short circuit event.
GND13GConnect to the system ground plane.
HGATE14OGATE driver output for the HSFET. Connect to the GATE of the external FET.
OUT15IConnect to the output rail (external MOSFET source).
SLEEP_OV16ISLEEP mode over voltage protection pin. Connect this pin to Vs for over voltage cut-off functionality. Connect to OUT for over voltage clamp functionality.
N.C.17—No connection. Keep this pin floating.
ISCP18I

Current sense negative input for adjustable short circuit protection. When ISCP is connected to output, device monitors external HFET voltage drop between CS+ and ISCP pins against an internal fix threshold of 50-mV typical.

CS–19ICurrent sense amplifier supply input.
CS+20ICurrent sense positive input for adjustable short circuit protection.
N.C.21—No connection. Keep this pin floating.
VS22PInput power supply to the IC. Connect VS to middle point of the common drain back to back MOSFET configuration. Connect a 100-nF capacitor across VS and GND pins.
CAP23OCharge pump output. Connect a 100-nF capacitor across CAP and VS pin.
C24ICathode of the ideal diode. Connect to the drain of the external MOSFET.
RTNThermal pad—Leave exposed pad floating. Do not connect to GND plane.
(1) I = input, O = output, I/O = input and output, P = power, G = ground