SNOSDE8A July   2023  – September 2023 LM74912-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump
      2. 8.3.2 Dual Gate Control (DGATE, HGATE)
        1. 8.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 8.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 8.3.3 Short Circuit Protection (CS+, CS-, ISCP)
      4. 8.3.4 Overvoltage Protection and Battery Voltage Sensing (SW, OV, UVLO)
      5. 8.3.5 Low IQ SLEEP Mode (SLEEP, SLEEP_OV)
    4. 8.4 Device Functional Modes
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Automotive Reverse Battery Protection
        1. 9.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
        2. 9.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
        3. 9.2.2.3 Input Micro-Short Protection: LV124 E-10
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Design Considerations
        2. 9.2.3.2 Charge Pump Capacitance VCAP
        3. 9.2.3.3 Input , Supply and Output Capacitance
        4. 9.2.3.4 Hold-Up Capacitance
        5. 9.2.3.5 Overvoltage Protection and Battery Monitor
        6. 9.2.3.6 Selecting Short Circuit Current Threshold
          1. 9.2.3.6.1 Selection of Scaling Resistor RSET and RISCP for Short Circuit Protection
      4. 9.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 9.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 9.2.6 TVS Selection
      7. 9.2.7 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 TVS Selection for 12-V Battery Systems
      3. 9.4.3 TVS Selection for 24-V Battery Systems
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) =  V(OUT) = V(VS) = 12 V, C(CAP) = 0.1 µF, V(EN) , V(SLEEP)= 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
V(VS) Operating input voltage 3 65 V
V(VS_PORR) VS POR threshold, rising 2.4 2.65 2.9 V
V(VS_PORF) VS POR threshold, falling 2.2 2.45 2.7 V
I(SHDN) SHDN current, I(GND) V(EN) = 0 V 2.5 5 µA
I(SLEEP) SLEEP mode current, I(GND) V(EN) = 2 V, V(SLEEP) = 0 V 5.5 10 µA
I(Q) Total system quiescent current, I(GND) V(EN) = 2 V 610 730 µA
V(A) = V(VS) = 24 V, V(EN) = 2 V 615 735 µA
I(REV) I(A)  leakage current during reverse polarity 0 V ≤ V(A) ≤ – 65 V –100 –35 µA
I(OUT) leakage current during reverse polarity –1 –0.3 µA
ENABLE
V(ENR) Enable threshold voltage for low Iq shutdown, rising 0.8 1.05 V
V(ENF) Enable falling threshold voltage for low Iq shutdown 0.41 0.7 V
I(EN) V(EN) = 65 V 55 200 nA
UNDERVOLTAGE LOCKOUT COMPARATOR
V(UVLOR) UVLO threshold voltage, rising 0.585 0.6 0.63 V
V(UVLOF) UVLO threshold voltage, falling 0.533 0.55 0.573 V
I(UVLO) UVLO pin leakage current 0 V ≤ V(UVLO) ≤ 5 V 52 200 nA
SLEEP MODE
V(SLEEPR) SLEEP threshold voltage for low IQ mode 0.8 1.05 V
V(SLEEPF) SLEEP threshold voltage for low Iq shutdown, falling 0.41 0.7 V
I(SLEEP) SLEEP input leakage current 0 V ≤ V(SLEEP) ≤ 12 V 100 160 nA
Overcurrent threshold SLEEP mode overcurrent threshold 150 250 310 mA
Overvoltage threshold Overvoltage comparator rising threshold 19.3 21.5 23 V
Overvoltage comparator falling threshold 18.4 21.04 22.2 V
FET resistance SLEEP mode bypass FET resistance 4.5 7.5 11.5 Ω
TSD Thermal shutdown rising threshold during SLEEP mode 155 ℃
OVERVOLTAGE PROTECTION AND BATTERY SENSING INPUT
R(SW) Battery sensing disconnect switch resistance 3 V ≤ V(SNS) ≤ 65 V 10 22 46 Ω
V(OVR) Overvoltage threshold input, rising 0.585 0.6 0.63 V
V(OVF) Overvoltage threshold input, falling 0.533 0.55 0.573 V
I(OV) OV pin Input leakage current 0 V ≤ V(OV) ≤ 5 V 52 200 nA
CURRENT SENSE AMPLIFIER
ICS+ CS+ pin sink current 10 11 11.85 µA
ISCP ISCP pin bias current 10 11 11.85 µA
V(SNS_SCP) Short circuit protection threshold RISCP = RSET = 0 Ω 47.3 50 53.4 mV
RSET = 1 kΩ, RISCP = 0 Ω 61 mV
RISCP = 1 kΩ, RSET = 0 Ω 39 mV
FAULT
R_FLT FLT pull-down resistance 11 25 60 Ω
I_FLT FLT pin leakage current –100 400 nA
CHARGE PUMP
I(CAP) Charge pump source current  V(CAP) – V(A) = 7 V, 6 V ≤ V(S) ≤ 65 V  2.5 4 mA
VCAP – VS Charge pump turn on voltage 11 12.2 13.2 V
Charge pump turn off voltage 11.9 13.2 14.1 V
V(CAP UVLO) Charge pump UVLO voltage threshold, rising 5.4 6.6 7.9 V
Charge pump UVLO voltage threshold, falling 4.4 5.4 6.6 V
IDEAL DIODE MOSFET CONTROL
V(A_PORR) V(A) POR threshold, rising 2.2 2.4 2.7 V
V(A_PORF) V(A) POR threshold, falling 2 2.2 2.45 V
V(AC_REG) Regulated forward V(A) – V(C) threshold 3.6 10.5 13.4 mV
V(AC_REV) V(A) – V(C) threshold for fast reverse current blocking –16 –10.5 –5 mV
V(AC_FWD) V(A) – V(C) threshold for reverse to forward transition 150 177 200 mV
V(DGATE) – V(A) Gate drive voltage 3 V < V(S) < 5 V 7 V
5 V < V(S) < 65 V 9.2 11.5 14 V
I(DGATE) Peak gate source current V(A) – V(C) = 300 mV, V(DGATE) – V(A) = 1 V 20 mA
Peak gate sink current V(A) – V(C) = –12 mV, V(DGATE) – V(A) = 11 V 2670 mA
Regulation sink current V(A) – V(C) = 0 V, V(DGATE) – V(A) = 11 V 6 15 µA
I(C) Cathode leakage current V(A) = –14 V, V(C) = 12 V 4 9 32 µA
HIGH SIDE MOSFET CONTROL
V(HGATE) – V(OUT) Gate drive voltage 3 V < V(S) < 5 V 7 V
5 V < V(S) < 65 V 10 11.1 14 V
I(HGATE) Source current 39 55 75 µA
Sink current 128 180 mA
V(HGATE –OUT)_SCP HGATE-OUT threshold for short circuit protection enable 6.4 V