SNOSDA7D September   2020  – March 2022 LMG3422R030 , LMG3425R030

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Times
      2. 8.1.2 Turn-Off Times
      3. 8.1.3 Drain-Source Turn-On Slew Rate
      4. 8.1.4 Turn-On and Turn-Off Switching Energy
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  GaN FET Operation Definitions
      2. 9.3.2  Direct-Drive GaN Architecture
      3. 9.3.3  Drain-Source Voltage Capability
      4. 9.3.4  Internal Buck-Boost DC-DC Converter
      5. 9.3.5  VDD Bias Supply
      6. 9.3.6  Auxiliary LDO
      7. 9.3.7  Fault Detection
        1. 9.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 9.3.7.2 Overtemperature Shutdown
        3. 9.3.7.3 UVLO Protection
        4. 9.3.7.4 Fault Reporting
      8. 9.3.8  Drive Strength Adjustment
      9. 9.3.9  Temperature-Sensing Output
      10. 9.3.10 Ideal-Diode Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slew Rate Selection
          1. 10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 10.2.2.2 Signal Level-Shifting
        3. 10.2.2.3 Buck-Boost Converter Design
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Solder-Joint Reliability
      2. 12.1.2 Power-Loop Inductance
      3. 12.1.3 Signal-Ground Connection
      4. 12.1.4 Bypass Capacitors
      5. 12.1.5 Switch-Node Capacitance
      6. 12.1.6 Signal Integrity
      7. 12.1.7 High-Voltage Spacing
      8. 12.1.8 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RQZ|54
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Ideal-Diode Mode Operation

Off-state FETs act like diodes by blocking current in one direction (first quadrant) and allowing current in the other direction (third quadrant) with a corresponding diode like voltage drop. FETs, though, can also conduct third-quadrant current in the on-state at a significantly lower voltage drop. Ideal-diode mode (IDM) is when an FET is controlled to block first-quadrant current by going to the off-state and conduct third-quadrant current by going to the on-state, thus achieving an ideal lower voltage drop.

FET off-state third-quadrant current flow is commonly seen in power converters, both in normal and fault situations. As explained in GaN FET Operation Definitions, GaN FETs do not have an intrinsic p-n junction body diode to conduct off-state third-quadrant current. Instead, the off-state third-quadrant voltage drop for the LMG342xR030 is several times higher than a p-n junction voltage drop, which can impact efficiency in normal operation and device ruggedness in fault conditions.

To mitigate efficiency degradation, the LMG3425R030 implements an operational ideal-diode mode (OP-IDM) function. Meanwhile, to improve device ruggedness in a GaN FET overtemperature fault situation, all devices in the LMG342xR030 family implement a GaN FET overtemperature-shutdown ideal-diode mode (OTSD-IDM) function as referenced in Overtemperature Shutdown. Both OP-IDM and OTSD-IDM are described in more detail below.

Operational Ideal-Diode Mode (LMG3425R030)

Operational ideal-diode mode (OP-IDM) is implemented in the LMG3425R030 but not in the LMG3422R030. Understand that the OP-IDM function is not a general-purpose ideal-diode mode function which allows the LMG342xR030 to autonomously operate as a diode, including as an autonomous synchronous rectifier. Furthermore, the OP-IDM function is not intended to support an ideal-diode mode transition from the on-state to the off-state in a high-voltage, hard-switched application. Exposing the LMG342xR030 to this situation is akin to operating a half-bridge power stage with negative dead time with corresponding high shoot-through current.

Instead, as described below, the LMG342xR030 OP-IDM function is narrowly implemented to address a specific off-state third-quadrant current flow situation while minimizing situations where the ideal-diode mode can create a dangerous shoot-through current event.

OP-IDM is intended to minimize GaN FET off-state third-quadrant losses that occur in a zero-voltage switched (ZVS) event. ZVS events are seen in applications such as synchronous rectifiers and LLC converters. The ZVS event occurs at the FET off-state to on-state transition when an inductive element discharges the FET drain voltage before the FET is turned-on. The discharge ends with the inductive element pulling the FET drain-source voltage negative and the FET conducting off-state third-quadrant current.

Power supply controllers use dead-time control to set the time for the ZVS event to complete before turning on the FET. Both the ZVS time and resulting FET off-state third-quadrant current are a function of the power converter operation. Long ZVS time and low third-quadrant current occur when the inductive element is slewing the FET with low current and short ZVS time and high third-quadrant current occur when the inductive element is slewing at the FET with high current. Sophisticated controllers optimally adjust the dead time to minimize third-quadrant losses. Simpler controllers use a fixed dead time to handle the longest possible ZVS time. Thus, in a fixed dead-time application, the highest possible off-state third-quadrant losses occur for the longest possible time.

OP-IDM mitigates the losses in a fixed dead-time application by automatically turning on the GaN FET as soon as third-quadrant current is detected. In this sense, OP-IDM can be described as providing a turn-on assist function with optimum dead-time control. Meanwhile, OP-IDM is not intended to be used to turn-off the GaN FET in normal operation. OP-IDM turnoff capability is only provided as a protection mechanism to guard against shoot-through current.

OP-IDM works within the confines of normal LMG342xR030 switching operation as controlled by the IN pin. The key consideration for the OP-IDM operation is to ensure the turn-on assist function is only activated on the ZVS edge. For example, third-quadrant current is seen in a LMG342xR030 used as a synchronous rectifier both before the IN pin goes high to turn on the GaN FET and after the IN pin goes low to turn off the GaN FET. OP-IDM turns on the GaN FET before the IN pin goes high when OP-IDM detects third-quadrant current. But it would be a mistake for OP-IDM to turn the GaN FET back on right after IN has turned it off because OP-IDM detects third-quadrant current. If OP-IDM were to turn on the GaN FET in this situation, it would create a shoot-through current event when the opposite-side power switch turns on. OP-IDM avoids this shoot-through current problem on the turn-off edge by requiring the drain voltage to first go positive before looking for the ZVS event.

The OP-IDM state machine is shown in Figure 9-4. Each state is assigned a state number in the upper right side of the state box.

Figure 9-4 Operational Ideal-Diode Mode (OP-IDM) State Machine
  1. A new OP-IDM cycle begins in OP-IDM state #1 after the IN pin goes low in OP-IDM state #5. OP-IDM turns off the GaN FET in OP-IDM state #1. OP-IDM monitors the GaN FET drain voltage, looking for a positive drain voltage to know it can now start looking for a ZVS event. After a positive GaN FET drain voltage is detected, the device moves to OP-IDM state #2.
  2. OP-IDM keeps the GaN FET off in OP-IDM state #2. OP-IDM continues monitoring the GaN FET drain voltage. But this time it is looking for a negative drain voltage which means third-quadrant current is flowing after a ZVS event. This is also the starting state when the device powers up or exits OTSD. After a negative GaN FET drain voltage is detected, the device moves to OP-IDM state #3.
  3. OP-IDM turns on the GaN FET in OP-IDM state #3. OP-IDM monitors the drain current in this state. Ideally, the device simply stays in this state until IN goes high. The drain current is monitored to protect against an unexpected shoot-through current event. If first-quadrant drain current is detected, the device moves to OP-IDM state #4.
  4. OP-IDM locks the GaN FET off in OP-IDM state #4. The GaN FET only turns back on when the IN pin goes high.
  5. The device moves to OP-IDM state #5 from any other state when the IN pin goes high. The GaN FET is commanded on in OP-IDM state #5. OP-IDM is idle in this state. A new OP-IDM switching cycle begins when IN goes low moving the device into OP-IDM state #1.

OP-IDM can only turn on the GaN FET once per IN cycle. If an unexpected shoot-through current is detected between OP-IDM turning on the GaN FET and the IN pin going high, OP-IDM locks the GaN FET off for the remainder of the IN cycle.

Understand that the OP-IDM function turns on the GaN FET, after IN goes low, if it sees a positive drain voltage followed by a negative drain voltage. A design using the LMG3425R030 must be analyzed for any situations where this sequence of events creates a shoot-through current event. The analysis must include all power system corner cases including start-up, shutdown, no load, overload, and fault events. Note that discontinuous mode conduction (DCM) operation can easily create an OP-IDM shoot-through current event when the ringing at the end of a DCM cycle triggers OP-IDM to turn on the GaN FET.

Overtemperature-Shutdown Ideal-Diode Mode

Overtemperature-shutdown ideal-diode mode (OTSD-IDM) is implemented in all devices in the LMG342xR030 family. As explained in Overtemperature Shutdown, ideal-diode mode provides the best GaN FET protection when the GaN FET is overheating.

OTSD-IDM accounts for all, some, or none of the power system operating when OTSD-IDM is protecting the GaN FET. The power system may not have the capability to shut itself down, in response to the LMG342xR030 asserting the FAULT pin in a GaN OTSD event, and just continue to try to operate. Parts of the power system can stop operating due to any reason such as a controller software bug or a solder joint breaking or a device shutting off to protect itself. At the moment of power system shutdown, the power system stops providing gate drive signals but the inductive elements continue to force current flow while they discharge.

The OTSD-IDM state machine is shown in Figure 9-5. Each state is assigned a state number in the upper right side of the state box. The OTSD-IDM state machine has a similar structure to the OP-IDM state machine. Similar states use the same state number.

Figure 9-5 Overtemperature-Shutdown Ideal-Diode Mode (OTSD-IDM) State Machine
  1. The LMG342xR030 GaN FET always goes to state #1 if a falling edge is detected on the IN pin. OTSD-IDM turns off the GaN FET in OTSD-IDM state #1. OTSD-IDM is waiting for the IN falling edge blank time to expire. This time gives the opposite-side FET time to switch to create a positive drain voltage. After the blank time expires, the device moves to OTSD-IDM state #2.
  2. For OTSD-IDM state #2, OTSD-IDM keeps the GaN FET off if it is coming from OTSD-IDM state #1 and turns the GaN FET off if it is coming from OTSD-IDM state #3. OTSD-IDM is monitoring the GaN FET drain voltage in OP-IDM state #2. It is looking for a negative drain voltage which means third-quadrant current is flowing. This is also the starting state when the device enters OTSD. After a negative GaN FET drain voltage is detected, the device moves to OTSD-IDM state #3
  3. OP-IDM turns on the GaN FET in OTSD-IDM state #3. OP-IDM monitors the drain current in this state. If first-quadrant drain current is detected, the device moves to OP-IDM state #2.

State #1 is used to protect against shoot-through current in a similar manner to OP-IDM state #1. The difference is that state #1 in the OTSD-IDM state machine simply waits for a fixed time period before proceeding to state #2. The fixed time period is to give the opposite-side switch time to switch and create a positive drain voltage. A fixed time is used to avoid a stuck condition for cases where a positive drain voltage is not created.

State #1 will help protect against shoot-through currents if the converter continues switching when the LMG342xR030 enters OTSD. Meanwhile, if the converter initiates switching with the LMG342xR030 already in OTSD, shoot-through current protection can be obtained by switching the OTSD device first to force it to progress though state #1. For example, the synchronous rectifier in a boost PFC can go into OTSD during initial input power application as the inrush current charges the PFC output cap. A shoot-through current event can be avoided if converter switching begins by switching the synchronous rectifier FET before switching the boost PFC FET.

If there is no IN signal, the state machine only moves between states #2 and #3 as a classic ideal-diode mode state machine. This allows all the inductive elements to discharge, when the power system shuts off, with minimum discharge stress created in the GaN FET.

Note that the OTSD-IDM state machine has no protection against repetitive shoot-through current events. There are degenerate cases, such as the LMG342xR030 losing its IN signal during converter operation, which can expose the OTSD-IDM to repetitive shoot-through current events. There is no good solution in this scenario. If OTSD-IDM did not allow repeated shoot-thru current events, the GaN FET would instead be exposed to excessive off-state third-quadrant losses.