SNOSDA7D September   2020  – March 2022 LMG3422R030 , LMG3425R030

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Switching Parameters
      1. 8.1.1 Turn-On Times
      2. 8.1.2 Turn-Off Times
      3. 8.1.3 Drain-Source Turn-On Slew Rate
      4. 8.1.4 Turn-On and Turn-Off Switching Energy
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  GaN FET Operation Definitions
      2. 9.3.2  Direct-Drive GaN Architecture
      3. 9.3.3  Drain-Source Voltage Capability
      4. 9.3.4  Internal Buck-Boost DC-DC Converter
      5. 9.3.5  VDD Bias Supply
      6. 9.3.6  Auxiliary LDO
      7. 9.3.7  Fault Detection
        1. 9.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 9.3.7.2 Overtemperature Shutdown
        3. 9.3.7.3 UVLO Protection
        4. 9.3.7.4 Fault Reporting
      8. 9.3.8  Drive Strength Adjustment
      9. 9.3.9  Temperature-Sensing Output
      10. 9.3.10 Ideal-Diode Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slew Rate Selection
          1. 10.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 10.2.2.2 Signal Level-Shifting
        3. 10.2.2.3 Buck-Boost Converter Design
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Using an Isolated Power Supply
    2. 11.2 Using a Bootstrap Diode
      1. 11.2.1 Diode Selection
      2. 11.2.2 Managing the Bootstrap Voltage
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Solder-Joint Reliability
      2. 12.1.2 Power-Loop Inductance
      3. 12.1.3 Signal-Ground Connection
      4. 12.1.4 Bypass Capacitors
      5. 12.1.5 Switch-Node Capacitance
      6. 12.1.6 Signal Integrity
      7. 12.1.7 High-Voltage Spacing
      8. 12.1.8 Thermal Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Export Control Notice
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RQZ|54
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overtemperature Shutdown

The LMG342xR030 implements two overtemperature-shutdown (OTSD) functions, the GaN OTSD and the Driver OTSD. Two OTSD functions are needed to maximize device protection by sensing different locations in the device and protecting against different thermal-fault scenarios.

The GaN OTSD senses the GaN FET temperature. The GaN FET can overheat from both first-quadrant current and third-quadrant current. As explained in GaN FET Operation Definitions, a FET can prevent first-quadrant current by going into the off-state but is unable to prevent third-quadrant current. FET third-quadrant losses are a function of the FET technology, current magnitude, and if the FET is operating in the on-state or off-state. As explained in GaN FET Operation Definitions, the LMG342xR030 has much higher GaN FET third-quadrant losses in the off-state.

When the GaN FET is too hot, the best protection is to turn off the GaN FET when first-quadrant current tries to flow and turn on the GaN FET when third-quadrant current is flowing. This type of FET control is known as ideal-diode mode (IDM). When the GaN OTSD trip point is exceeded, the GaN OTSD puts the GaN FET into overtemperature-shutdown ideal-diode mode (OTSD-IDM) operation to achieve this optimum protection. OTSD-IDM is explained in Ideal-Diode Mode Operation.

The Driver OTSD senses the integrated driver temperature and trips at a higher temperature compared to the GaN OTSD. This second OTSD function exists to protect the LMG342xR030 from driver thermal-fault events while allowing sufficient temperature difference for OTSD-IDM to operate. These driver thermal events include shorts on the LD05V, BBSW, and VNEG device pins. When the Driver OTSD trip point is exceeded, the Driver OTSD shuts off the LDO5V regulator, the VNEG buck-boost converter, and the GaN FET. Note that OTSD-IDM does not function in Driver OTSD. This is why the Driver OTSD must trip higher than the GaN OTSD function. Otherwise, GaN FET third-quadrant overheating cannot be addressed.

Besides the temperature difference in the GaN OTSD and Driver OTSD trip points, further temperature separation is obtained due to the thermal gradient difference between the GaN OTSD and Driver OTSD sense points. The GaN OTSD sensor is typically at least 20°C hotter than the driver OTSD sensor when the device is in GaN OTSD due to GaN FET power dissipation.

The FAULT pin is asserted for either or both the GaN OTSD state and the Driver OTSD state. FAULT de-asserts and the device automatically returns to normal operation after both the GaN OTSD and Driver OTSD fall below their negative-going trip points. During cool down, when the device exits the Driver OTSD state but is still in the GaN OTSD state, the device automatically resumes OTSD-IDM operation.