The power loop, comprising the two devices in the half bridge and the high-voltage bus capacitance, undergoes high di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-magnetic interference (EMI) can be reduced, as well as reducing voltage stress on the devices.
Place the power devices as close as possible to minimize the power-loop inductance. The decoupling capacitors are positioned in line with the two devices. They can be placed close to either device. In Layout Examples, the decoupling capacitors are placed on the same layer as the devices. The return path (PGND in this case) is located on second layer in close proximity to the top layer. By using inner layer and not bottom layer, the vertical dimension of the loop is reduced, thus minimizing inductance. A large number of vias near both the device terminal and bus capacitance carries the high-frequency switching current to inner layer while minimizing impedance.