8.2.1.1 Design Requirements
In the example application shown in Figure 10, the LMK00105 is used to fan-out a 3.3-V LVCMOS oscillator to three receiver devices with the following characteristics:
- The CPU input accepts a DC-coupled 3.3-V LVCMOS input clock. The LMK00105 has an internal 50-Ω series termination, thus the receiver is connected directly to the output.
- The FPGA input also requires a 3.3-V LVCMOS input clock, like the CPU.
- The PLL input requires a single-ended voltage swing less than 2 Vpp, so 1.8-V LVCMOS input signaling is needed. The PLL receiver requires AC coupling since it has internal input biasing to set its own common mode voltage level.