SNAS805 June 2020 LMK61E08
PRODUCTION DATA.
The PLL_CALCTRL register is described in the following table.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION | |
---|---|---|---|---|---|---|
[7:4] | RESERVED | - | - | N | Reserved. | |
[3:2] | PLL_CLSDWAIT[1:0] | RW | 0x2 | Y | Closed Loop Wait Period. The CLSDWAIT field sets the closed loop wait period. Recommended value is 0x2. | |
CLSDWAIT | Anlog closed loop VCO stabilization time | |||||
0 (0x0) | 150 µs | |||||
1 (0x1) | 300 µs | |||||
2 (0x2) | 500 µs | |||||
3 (0x3) | 2000 µs | |||||
[1:0] | PLL_VCOWAIT[1:0] | RW | 0x1 | Y | VCO Wait Period. Recommended value is 0x1. | |
VCOWAIT | VCO stabilization time | |||||
0 (0x0) | 20 µs | |||||
1 (0x1) | 400 µs | |||||
2 (0x2) | 4000 µs | |||||
3 (0x3) | 10000 µs |