The LMK61E08 family of ultra-low jitter PLLatinum™ programmable oscillators uses fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E08 can be configured as LVPECL, LVDS, or HCSL. The device features self-start-up from on-chip EEPROM to generate a factory-programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through an I2C serial interface. The device provides fine and coarse frequency margining control through an I2C serial interface, making it a digitally-controlled oscillator (DCXO).
The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | LMK61E08 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM datasheet | PDF | HTML | Jun 24, 2020 |
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The LMK61E2EVM evaluation modules provides a complete platform to evaluate the 90-fs RMS jitter performance and configurability of the Texas Instruments LMK61E2 Ultra-Low Jitter Programmable Differential Oscillator with integrated EEPROM and frequency margining capabilities.
The LMK61E2EVM can be (...)
Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| QFM (SIA) | 6 | Ultra Librarian |
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