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LMK61E08

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Ultra-low jitter programmable oscillator with internal EEPROM

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Product details

Parameters

Features Ultra-Low Jitter Fully Programmable Oscillator, Integrated EEPROM, +/-25ppm Output frequency (Max) (MHz) 1000 Output level HCSL, LVDS, LVPECL Jitter (ps) 0.09 Stability (ppm) 25 Core supply voltage (V) 3.3 Operating temperature range (C) -40 to 85 open-in-new Find other Oscillators

Package | Pins | Size

QFM (SIA) 6 open-in-new Find other Oscillators

Features

  • Ultra-Low Noise, High Performance
    • Jitter: 90-fs RMS Typical fOUT > 100 MHz on LMK61E08
    • PSRR: –70 dBc, Robust Supply Noise Immunity on LMK61E08
  • Flexible Output Format on LMK61E08
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±25 ppm
  • System Level Features
    • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
    • Internal EEPROM: User Configurable Start-Up Settings
  • Other Features
    • Device Control: Fast Mode I2C up to 1000 kHz
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 6-Pin Package
  • Default Frequency:
    • 70.656 MHz

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Description

The LMK61E08 family of ultra-low jitter PLLatinum™ programmable oscillators uses fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E08 can be configured as LVPECL, LVDS, or HCSL. The device features self-start-up from on-chip EEPROM to generate a factory-programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through an I2C serial interface. The device provides fine and coarse frequency margining control through an I2C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

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Technical documentation

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Type Title Date
* Datasheet LMK61E08 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM datasheet Jun. 24, 2020
Technical articles How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015

Design & development

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Hardware development

EVALUATION BOARDS Download
document-generic User guide
99
Description

The LMK61E2EVM evaluation modules provides a complete platform to evaluate the 90-fs RMS jitter performance and configurability of the Texas Instruments LMK61E2 Ultra-Low Jitter Programmable Differential Oscillator with integrated EEPROM and frequency margining capabilities.

The LMK61E2EVM can be (...)

Features
  • Ultra low jitter differential clock generation
  • Powered over USB or externally (SMA connector)
  • Onboard USB to I2C interface
  • Coarse and Fine Frequency margining
  • GUI platform for full access to LMK03328 registers and EEPROM

Design tools & simulation

SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
QFM (SIA) 6 View options

Ordering & quality

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