Home Clocks & timing Oscillators
Home
Clocks & timing
Oscillators

LMK61E08

ACTIVE

Ultra-low jitter programmable oscillator with internal EEPROM

Order now
Data sheet

LMK61E08

ACTIVE
Data sheet Order now

Product details

Features Programmable frequency Output frequency (MHz) 1000 Output type HCSL, LVDS, LVPECL Stability (ppm) 25 Supply voltage (V) 3.3 Jitter (ps) 0.09 Operating temperature range (°C) -40 to 85 Rating Catalog
Features Programmable frequency Output frequency (MHz) 1000 Output type HCSL, LVDS, LVPECL Stability (ppm) 25 Supply voltage (V) 3.3 Jitter (ps) 0.09 Operating temperature range (°C) -40 to 85 Rating Catalog
QFM (SIA) 6 35 mm² 7 x 5
  • Ultra-Low Noise, High Performance
    • Jitter: 90-fs RMS Typical fOUT > 100 MHz on LMK61E08
    • PSRR: –70 dBc, Robust Supply Noise Immunity on LMK61E08
  • Flexible Output Format on LMK61E08
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±25 ppm
  • System Level Features
    • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
    • Internal EEPROM: User Configurable Start-Up Settings
  • Other Features
    • Device Control: Fast Mode I2C up to 1000 kHz
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 6-Pin Package
  • Default Frequency:
    • 70.656 MHz
  • Ultra-Low Noise, High Performance
    • Jitter: 90-fs RMS Typical fOUT > 100 MHz on LMK61E08
    • PSRR: –70 dBc, Robust Supply Noise Immunity on LMK61E08
  • Flexible Output Format on LMK61E08
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±25 ppm
  • System Level Features
    • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
    • Internal EEPROM: User Configurable Start-Up Settings
  • Other Features
    • Device Control: Fast Mode I2C up to 1000 kHz
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 6-Pin Package
  • Default Frequency:
    • 70.656 MHz

The LMK61E08 family of ultra-low jitter PLLatinum™ programmable oscillators uses fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E08 can be configured as LVPECL, LVDS, or HCSL. The device features self-start-up from on-chip EEPROM to generate a factory-programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through an I2C serial interface. The device provides fine and coarse frequency margining control through an I2C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

The LMK61E08 family of ultra-low jitter PLLatinum™ programmable oscillators uses fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E08 can be configured as LVPECL, LVDS, or HCSL. The device features self-start-up from on-chip EEPROM to generate a factory-programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through an I2C serial interface. The device provides fine and coarse frequency margining control through an I2C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.
open-in-new Find other Oscillators
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Same functionality with different pin-out to the compared device
NEW LMK6D ACTIVE Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVDS oscillator Small package, improved performance, fixed-frequency LVDS oscillator with BAW technology
NEW LMK6H ACTIVE Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency HCSL oscillator Small package, improved performance, fixed-frequency HCSL oscillator with BAW technology
NEW LMK6P ACTIVE Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVPECL oscillator Small package, improved performance, fixed-frequency LVPECL oscillator with BAW technology

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet LMK61E08 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM datasheet PDF | HTML 24 Jun 2020
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK61E2EVM — LMK61E2EVM Ultra-Low-Jitter Programmable Oscillator Evaluation Module

The LMK61E2EVM evaluation modules provides a complete platform to evaluate the 90-fs RMS jitter performance and configurability of the Texas Instruments LMK61E2 Ultra-Low Jitter Programmable Differential Oscillator with integrated EEPROM and frequency margining capabilities.

The LMK61E2EVM can be (...)

User guide: PDF
Not available on TI.com
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design now
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins Download
QFM (SIA) 6 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos