SNAS805 June 2020 LMK61E08
PRODUCTION DATA.
The PLL_CTRL1 register provides control of PLL. The PLL_CTRL1 register fields are described in the following table.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION | |
---|---|---|---|---|---|---|
[7:6] | RESERVED | RW | 0x0 | Y | Reserved. | |
[5] | PLL_D | RW | 1 | Y | PLL R Divider Frequency Doubler Enable. If PLL_D is 1 the R Divider Frequency Doubler is enabled. | |
[4] | RESERVED | - | - | N | Reserved. | |
[3:0] | PLL_CP[3:0] | RW | 0x4 | Y | PLL Charge Pump Current. Other combinations of PLL_CP[3:0] not in table below are reserved and not supported. | |
PLL_CP[3:0] | PLL Charge Pump Current | |||||
4 (0x4) | 1.6 mA | |||||
8 (0x8) | 6.4 mA |