SNAS826E April   2022  – April 2024 LMK6C , LMK6D , LMK6H , LMK6P

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Ordering Information
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Environmental Compliance
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bulk Acoustic Wave (BAW)
      2. 8.3.2 Device Block-Level Description
      3. 8.3.3 Function Pins
      4. 8.3.4 Clock Output Interfacing and Termination
      5. 8.3.5 Temperature Stability
      6. 8.3.6 Mechanical Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Providing Thermal Reliability
        2. 9.4.1.2 Recommended Solder Reflow Profile
      2. 9.4.2 Layout
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4 Clock Output Interfacing and Termination

These figures show the recommended output interfacing and termination circuits.

GUID-20220404-SS0I-3NVS-336L-GTS4ZNBKDTBN-low.svgFigure 8-1 LMK6C Output to LVCMOS Receiver
GUID-20220404-SS0I-1J9K-3X1J-9JMMZNRXTHSD-low.svg Figure 8-2 LMK6D Output DC-Coupled to LVDS Receiver With Internal Termination/Biasing
GUID-20220404-SS0I-NKZH-P2JN-DXC6BTX81WPJ-low.svg Figure 8-3 LMK6D Output AC Coupled to LVDS Receiver With Internal Termination/Biasing
GUID-20220404-SS0I-6HCC-SS4H-2JH70MGCD1BS-low.svgFigure 8-4 LMK6P Output DC-Coupled to LVPECL Receiver With External Termination/Biasing
(T-Network)
Table 8-3 LMK6P T-Network DC-Coupled Resistor Values
SUPPLY (V) R1 (Ω) R2 (Ω)
3.3 133 82
2.5 250 62.5
1.8 450 56.5

GUID-20220404-SS0I-79PS-7N93-92SNTPFGFLNQ-low.svgFigure 8-5 LMK6P Output AC-Coupled to LVPECL Receiver With External Termination/Biasing
(T-Network)
Table 8-4 LMK6P T-Network AC-Coupled Resistor Values
SUPPLY (V) Rp (Ω) R1 (Ω) R2 (Ω)
3.3 207.5 133 82
2.5 112.5 250 62.5
1.8 83.3 450 56.6

GUID-20220404-SS0I-WZZC-C7LT-ZTCB7WPDZ3XJ-low.svgFigure 8-6 LMK6P Output DC-Coupled to LVPECL Receiver With External Termination/Biasing
(Y-Network)
Table 8-5 LMK6P Y-Network DC-Coupled Resistor Values
SUPPLY (V) R1 (Ω) R2 (Ω)
3.3 50 78.8
2.5 50 31.3
1.8 50 16.7

GUID-20220404-SS0I-7RV7-986X-F6CHWGSHZNJF-low.svgFigure 8-7 LMK6P Output AC-Coupled to LVPECL Receiver With External Termination/Biasing
(Y-Network)
Table 8-6 LMK6P Y-Network AC-Coupled Resistor Values
SUPPLY (V) Rp (Ω) R1 (Ω) R2 (Ω)
3.3 207.5 50 78.8
2.5 112.5 50 31.3
1.8 83.3 50 16.7

GUID-20220717-SS0I-LTF5-HPL5-FMZNVRN3PQNF-low.svg Figure 8-8 LMK6H Output to HCSL Receiver With External Termination
GUID-20220718-SS0I-BXVL-PGS5-7QQNWWQDQKQ8-low.svg Figure 8-9 LMK6H Output AC-Coupled to HCSL Receiver With External Termination