SNVSBU3 March   2021 LP87702


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Step-Down DC/DC Converters
        1. Overview
        2. Transition Between PWM and PFM Modes
        3. Buck Converter Load Current Measurement
      2. 7.3.2  Boost Converter
      3. 7.3.3  Spread-Spectrum Mode
      4. 7.3.4  Sync Clock Functionality
      5. 7.3.5  Power-Up
      6. 7.3.6  Buck and Boost Control
        1. Enabling and Disabling Converters
        2. Changing Buck Output Voltage
      7. 7.3.7  Enable and Disable Sequences
      8. 7.3.8  Window Watchdog
      9. 7.3.9  Device Reset Scenarios
      10. 7.3.10 Diagnostics and Protection Features
        1. Voltage Monitorings
        2. Interrupts
        3. Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. PGx Pin Gated (Unusual) Mode
          2. PGx Pin Operation in Continuous Mode
          3. Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. Warning Interrupts for System Level Diagnostics
          1. Output Power Limit
          2. Thermal Warning
        5. Protections Causing Converter Disable
          1. Short-Circuit and Overload Protection
          2. Overvoltage Protection
          3. Thermal Shutdown
        6. Protections Causing Device Power Down
          1. Undervoltage Lockout
      11. 7.3.11 OTP Error Correction
      12. 7.3.12 Operation of GPO Signals
      13. 7.3.13 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. Data Validity
        2. Start and Stop Conditions
        3. Transferring Data
        4. I2C-Compatible Chip Address
        5. Auto Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. LP8770_map Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Application Components
          1. Inductor Selection
          2. Buck Input Capacitor Selection
          3. Buck Output Capacitor Selection
          4. Boost Input Capacitor Selection
          5. Boost Output Capacitor Selection
          6. Supply Filtering Components
      3. 8.2.3 Current Limit vs Maximum Output Current
      4. 8.2.4 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Buck Output Capacitor Selection

Section 8.2 shows the output capacitor COUT0 and COUT1. A ceramic local output capacitor of 22 μF is required for both outputs. Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out the current flow from the inductor to the load, whic helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance for good performance is 15 μF for each buck, including the DC voltage roll-off, tolerances, aging, and temperature effects.

The output voltage ripple is caused by charging and discharging the output capacitor, and is also due to its RESR. Table 8-5 shows how the RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the part's switching frequency.

POL capacitors can be used to improve load transient performance and to decrease the ripple voltage. A higher output capacitance improves the load step behavior, reduces the output voltage ripple, and decreases the PFM switching frequency. Note: the output capacitor may be the limiting factor in the output voltage ramp, especially for very large (100-μF range) output capacitors. The output voltage might be slower than the programmed ramp rate at voltage transitions for large output capacitors, because of the higher energy stored on the output capacitance. Also, the time required to charge the output capacitor to target value might be longer at start-up. The output voltage is discharged to 0.6 V level using forced-PWM operation at shutdown. This can increase the input voltage if the load current is small and the output capacitor is large compared to the input capacitor. The output capacitor is discharged by the internal discharge resistor when below the 0.6 V level, and more time is required to settle VOUT down with a large capacitor because of the increased time constant.

Table 8-5 Recommended Buck Output Capacitors (X7R or X7T Dielectric)
Murata GRM21BD71A226ME44 22 µF (10%) 0805 2 × 1.25 × 1.25 10 V
TDK C2012X7S1A226M125AC 22 µF (20%) 0805 2 × 1.25 × 1.25 10 V