SNVSBU3 March   2021 LP87702

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Step-Down DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
      2. 7.3.2  Boost Converter
      3. 7.3.3  Spread-Spectrum Mode
      4. 7.3.4  Sync Clock Functionality
      5. 7.3.5  Power-Up
      6. 7.3.6  Buck and Boost Control
        1. 7.3.6.1 Enabling and Disabling Converters
        2. 7.3.6.2 Changing Buck Output Voltage
      7. 7.3.7  Enable and Disable Sequences
      8. 7.3.8  Window Watchdog
      9. 7.3.9  Device Reset Scenarios
      10. 7.3.10 Diagnostics and Protection Features
        1. 7.3.10.1 Voltage Monitorings
        2. 7.3.10.2 Interrupts
        3. 7.3.10.3 Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. 7.3.10.3.1 PGx Pin Gated (Unusual) Mode
          2. 7.3.10.3.2 PGx Pin Operation in Continuous Mode
          3. 7.3.10.3.3 Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. 7.3.10.4 Warning Interrupts for System Level Diagnostics
          1. 7.3.10.4.1 Output Power Limit
          2. 7.3.10.4.2 Thermal Warning
        5. 7.3.10.5 Protections Causing Converter Disable
          1. 7.3.10.5.1 Short-Circuit and Overload Protection
          2. 7.3.10.5.2 Overvoltage Protection
          3. 7.3.10.5.3 Thermal Shutdown
        6. 7.3.10.6 Protections Causing Device Power Down
          1. 7.3.10.6.1 Undervoltage Lockout
      11. 7.3.11 OTP Error Correction
      12. 7.3.12 Operation of GPO Signals
      13. 7.3.13 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1 LP8770_map Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Application Components
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Buck Input Capacitor Selection
          3. 8.2.2.1.3 Buck Output Capacitor Selection
          4. 8.2.2.1.4 Boost Input Capacitor Selection
          5. 8.2.2.1.5 Boost Output Capacitor Selection
          6. 8.2.2.1.6 Supply Filtering Components
      3. 8.2.3 Current Limit vs Maximum Output Current
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.10.1 Voltage Monitorings

The LP87702 device has programmable voltage monitoring for the BUCKx and BOOST converter output voltages and for VANA, VMON1, and VMON2 inputs. Monitoring of each signal is independently enabled in the PGOOD_CTRL register. Voltage monitoring can be under-voltage monitoring only (PGOOD_WINDOW = 0) or overvoltage and undervoltage monitoring (PGOOD_WINDOW = 1). This selection is common for all enabled monitorings. Section 7.3.10.3describes how the enabled monitoring signals are combined to generate power-good (PG0 and PG1) and interrupts. Monitoring comparators have a dedicated reference and bias block, which is independent of the main reference and bias block.

Nominal level for the output voltage of BUCKx converter is set with BUCKx_VSET in the BUCKx_VOUT register. Overvoltage and undervoltage detection levels, with respect to nominal level, are selected with BUCKx_WINDOW as ± 30 mV, ± 50 mV, ± 70 mV or ± 90 mV. Nominal level for the output voltage of the BOOST converter is set with BOOST_VSET in the BOOST_CTRL register. Available levels are 4.9 V, 5 V, 5.1 V, and 5.2 V. Overvoltage and undervoltage detection levels, with respect to nominal level, are selected with BOOST_WINDOW as ± 2%, ± 4%, ± 6% or ± 8%. Converter monitoring window selection bits are in the PGOOD_LEVEL_3 register.

Input voltage of LP87702 is monitored at the VANA pin. Nominal level can be selected as 3.3 V or 5 V with the VANA_THRESHOLD bit. Overvoltage and undervoltage detection levels are selected with VANA_WINDOW as (nominal). VANA_THRESHOLD and VANA_WINDOW are set in the PGOOD_LEVEL_2 register.

VMON1 and VMON2 inputs can be used for monitoring external rails in the system. VMONx settings are defined in the PGOOD_LEVEL_1 and PGOOD_LEVEL_2 registers. Nominal value for the input level of VMONx is selected with VMONx_THRESHOLD, between 0.65 V to 1.8 V. Higher voltage levels or levels not directly supported can be monitored using an external resistor divider. In this case VMONx_THRESHOLD must be set as 0.65 V to have a high-impedance input, and the resistor divider must scale the monitored level down to 0.65 V at the VMONx pin. Overvoltage and undervoltage detection levels are selected with VMONx_WINDOW as ± 2%, ± 3%, ± 4% or ± 6%.

See Section 6 for more details on the accuracy of the monitoring windows and deglitch filtering.