SNVSBU3 March 2021 LP87702
Figure 7-8 shows the LP87702 watchdog's operation (for an example, when the ENx pin is used for controlling power sequence and ENx pin is active).
WDI is the watchdog function input pin, and WD_RESET is the reset output. The WDI pin needs pulsed within a certain timing window to avoid a watchdog expiration. The minimum pulse width is 100 µs. The watchdog expiration always causes a reset pulse at WD_RESET output, otherwise the device behavior after watchdog expiration is programmable. WD_RESET output polarity and mode, push-pull or open drain, are also programmable.
Watchdog default settings are read from OTP during device start-up. Default settings in WD_CTRL_1 and WD_CTRL_2 register can be over-written through the I2C (as long as WD_LOCK bit is not set to 1). Writing WD_LOCK = 1 in WD_CTRL_2 register locks watchdog settings until NRST input is driven low, power cycle or register reset by SW_RESET.
Table 7-4 shows how the long open, close, and open window periods are independently programmable. The watchdog enters the WD Reset state when the long open or open window expires before the WDI input is received. Also, the watchdog enters the WD Reset when the WDI is received during close window. Long open period can be extended by a I2C write to WD_CTRL_1 or WD_CTRL_2 register; the register access initializes the long open counter and the long open period restarts (except in Stop mode).
LP87702 behavior after WD expiration is programmable:
Watchdog settings in WD_CTRL_1 and WD_CTRL_2 registers are locked by setting the WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK = 1.
Description above is for a case where ENx pin is used for controlling power sequence and ENx pin is active. Watchdog behavior can be slightly different depending on the OTP settings and the ENx pin state, which follows:
|WD_LONG_OPEN_TIME||OTP||00 – 200 ms |
01 – 600 ms
10 – 2000 ms
11 – 5000 ms
|WD_CLOSE_TIME||OTP||00 – 10 ms |
01 – 20 ms
10 – 50 ms
11 – 100 ms