SNVSBU3 March   2021 LP87702

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Step-Down DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
      2. 7.3.2  Boost Converter
      3. 7.3.3  Spread-Spectrum Mode
      4. 7.3.4  Sync Clock Functionality
      5. 7.3.5  Power-Up
      6. 7.3.6  Buck and Boost Control
        1. 7.3.6.1 Enabling and Disabling Converters
        2. 7.3.6.2 Changing Buck Output Voltage
      7. 7.3.7  Enable and Disable Sequences
      8. 7.3.8  Window Watchdog
      9. 7.3.9  Device Reset Scenarios
      10. 7.3.10 Diagnostics and Protection Features
        1. 7.3.10.1 Voltage Monitorings
        2. 7.3.10.2 Interrupts
        3. 7.3.10.3 Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. 7.3.10.3.1 PGx Pin Gated (Unusual) Mode
          2. 7.3.10.3.2 PGx Pin Operation in Continuous Mode
          3. 7.3.10.3.3 Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. 7.3.10.4 Warning Interrupts for System Level Diagnostics
          1. 7.3.10.4.1 Output Power Limit
          2. 7.3.10.4.2 Thermal Warning
        5. 7.3.10.5 Protections Causing Converter Disable
          1. 7.3.10.5.1 Short-Circuit and Overload Protection
          2. 7.3.10.5.2 Overvoltage Protection
          3. 7.3.10.5.3 Thermal Shutdown
        6. 7.3.10.6 Protections Causing Device Power Down
          1. 7.3.10.6.1 Undervoltage Lockout
      11. 7.3.11 OTP Error Correction
      12. 7.3.12 Operation of GPO Signals
      13. 7.3.13 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1 LP8770_map Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Application Components
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Buck Input Capacitor Selection
          3. 8.2.2.1.3 Buck Output Capacitor Selection
          4. 8.2.2.1.4 Boost Input Capacitor Selection
          5. 8.2.2.1.5 Boost Output Capacitor Selection
          6. 8.2.2.1.6 Supply Filtering Components
      3. 8.2.3 Current Limit vs Maximum Output Current
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ 140°C, specified VVANA, VVIN_Bx, VVOUT_Bx, VVOUT_BST, and IOUT range, unless otherwise noted. Typical values are at TA = 25°C, VVANA = VVIN_Bx = 3.3 V, VOUT_BST = 5 V and VOUT_Bx = 1 V, unless otherwise noted. (1) (2)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
EXTERNAL COMPONENTS
CIN_BUCKInput filtering capacitance for buck convertersEffective capacitance, connected from VIN_Bx to PGND_Bx1.910µF
COUT_BUCKOutput filtering capacitance for buck convertersEffective total capacitance. Maximum includes POL capacitance1522100µF
COUT_BUCK_POLPoint-of-load (POL) capacitance for buck convertersOptional POL capacitance22µF
COUT_BSTOutput filtering capacitance for boost converterEffective capacitance102240µF
ESRCInput and output capacitor ESR[1-10] MHz210mΩ
LBUCKInductor for buck convertersInductance of the inductor0.47µH
–30%30%
LBSTInductor for boost convertersInductance of the inductor, 2-MHz switching1µH
Inductance of the inductor, 4-MHz switching1
Inductance of the inductor–30%30%
DCRLInductor DCR25mΩ
BUCK CONVERTERS
V(VIN_Bx), V(VANA)Input voltage range2.83.35.5V
VOUT_BxOutput voltageProgrammable voltage range0.713.36V
Step size, 0.7 V ≤ VOUT < 0.73 V10mV
Step size, 0.73 V ≤ VOUT < 1.4 V5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V20
IOUT_BxOutput currentOutput current3.5 (3)A
Minimum voltage difference between V(VIN_Bx) and VOUT_Bx for electrical characteristics V(VIN_Bx) – VOUT, IOUT_Bx  ≤ 2 A 0.8 V
V(VIN_Bx) – VOUT, IOUT_Bx  > 2 A1
DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperatureForce PWM mode, VOUT ˂ 1.0 V–2020mV
Force PWM mode, VOUT ≥ 1.0 V–2% 2%
PFM mode, VOUT ˂ 1.0 V, the average output voltage level is increased by max. 20 mV–2040mV
PFM mode, VOUT ≥ 1.0 V, the average output voltage level is increased by max. 20 mV–2%2% + 20mV
Ripple voltagePWM mode, VOUT = 1.2 V, fSW = 4 MHz, COUT = 22 + 22 µF (GCM31CR71A226KE02)5mVp-p
PFM mode, L = 0.47 µH, COUT = 22 + 22 µF (GCM31CR71A226KE02)25
DCLNRDC line regulationIOUT = IOUT(max)±0.05%/V
DCLDRDC load regulation in PWM modeVOUT_Bx = 1.0 V, IOUT from 0 to IOUT(max)0.3%
TLDSRTransient load step responseIOUT = 0 A to 3 A, TR = TF = 1 µs, PWM mode, VVIN_Bx = 3.3V, VOUT_Bx = 1.2 V, COUT = 22 + 22 µF, L = 0.47 µH, fSW = 4 MHz±65mV
TLNSRTransient line responseV(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max)±20mV
ILIM FWDForward current limit for both bucks (peak for every switching cycle)Programmable range1.54.5A
Step size0.5
Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A–5%7.5%20%
Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A–20%7.5%20%
ILIM NEGNegative current limit1.623A
RDS(ON) BUCK HS FETOn-resistance, high-side FETEach phase, between VIN_Bx and SW_Bx pins (I = 1.0 A)60110mΩ
RDS(ON) BUCK LS FETOn-resistance, low-side FETEach phase, between SW_Bx and PGND_Bx pins (I = 1.0 A)5580mΩ
ƒSWSwitching frequency, PWM mode
OTP programmable		2-MHz setting or VOUT_Bx < 0.8 V1.822.2MHz
3-MHz setting and VOUT_Bx ≥ 0.8 V2.733.3
4-MHz setting and VOUT_Bx ≥ 1.1 V3.644.4
Start-up time (soft start)From ENx to VOUT_Bx = 0.35 V (slew-rate control begins)120µs
Overshoot during start-up50mV
Output voltage slew-rate(4)SLEW_RATEx[2:0] = 010, VVOUT_Bx ≥ 0.7 V–15%1015%mV/µs
Output voltage slew-rate(4)SLEW_RATEx[2:0] = 011, VVOUT_Bx ≥ 0.7 V–15%7.515%mV/µs
Output voltage slew-rate(4)SLEW_RATEx[2:0] = 100, VVOUT_Bx ≥ 0.7 V–15%3.815%mV/µs
Output voltage slew-rate(4)SLEW_RATEx[2:0] = 101, VVOUT_Bx ≥ 0.7 V–15%1.915%mV/µs
Output voltage slew-rate(4)SLEW_RATEx[2:0] = 110, VVOUT_Bx ≥ 0.7 V–15%0.9415%mV/µs
Output voltage slew-rate(4)SLEW_RATEx[2:0] = 111, VVOUT_Bx ≥ 0.7 V–15%0.4715%mV/µs
IPFM-PWMPFM-to-PWM switch - current threshold(5)520mA
IPWM-PFMPWM-to-PFM switch - current threshold(5)240mA
Output pull-down resistanceConverter disabled75125175Ω
BOOST CONVERTER
VIN_BSTInput voltage range for boost power inputs2.83.34V
Input voltage range when bypass switch mode selected4.55.5V
VOUT_BSTOutput voltage, boost modeBOOST_VSET = 004.9V
BOOST_VSET = 015.0
BOOST_VSET = 105.1
BOOST_VSET = 115.2
IOUT_BSTOutput currentBoth boost and bypass mode0.6A
ILIM_BSTOutput current limitBOOST_ILIM = 00, VIN_BST < 3.6 V0.811.3A
BOOST_ILIM = 01, VIN_BST < 3.6 V1.11.41.9
BOOST_ILIM = 10, VIN_BST < 3.6 V1.51.92.3
BOOST_ILIM = 11, VIN_BST < 3.6 V2.22.83.4
VOUT_BST_DCDC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature. Boost modeDefault output voltage–3%3%
VDROPVoltage drop, bypass mode,Iout = 250 mA83mV
Ripple voltage, boost mode22 µF effective output capacitance20mVp-p
DCLDRDC load regulation, boost modeIOUT = 1 mA to IOUT(max)0.3%
TLDSRTransient load step response, boost modeIOUT = 1 mA to 250 mA, TR = TF = 1 µs, 22 µF effective output capacitance, VIN > 3 V–220220mV
ISHORTShort circuit current limitationDuring start-up, both boost and bypass mode. Short circuit current limit applies until VOUT_BST = VIN_BST625mA
RDS(ON) BST HS FETOn-resistance, high-side FETPin-to-pin, between SW_BST and VOUT_BST pins (I = 250 mA)145220mΩ
RDS(ON) BST LS FETOn-resistance, low-side FETPin-to-pin, between SW_BST and PGND_BST pins (I = 250 mA)90175mΩ
ƒSWSwitching frequency, boost mode2-MHz setting1.822.2MHz
4-MHz setting3.644.4MHz
Start-up time, boost modeFrom enable to boost VOUT within 3% of target value. COUT_BST = 22 µF450µs
Output pull-down resistanceConverter disabled135Ω
EXTERNAL CLOCK AND PLL
External input clock(6)Nominal frequency124MHz
Nominal frequency step size1
Required accuracy from nominal frequency–30%10%
External clock detectionDelay for detecting loss of external clock, nominal internal clock, clock accuracy ±10%1.8µs
Delay for detecting valid external clock, nominal internal clock, clock accuracy ±10%20
Clock change delay (internal to external)Delay from valid clock detection to use of external clock600µs
PLL output clock jitterCycle to cycle300ps, p-p
MONITORING FUNCTIONS
VANA Voltage MonitoringVoltage threshold, VANA_THRESHOLD = 03.3V
Voltage threshold, VANA_THRESHOLD = 15.0
Voltage window, VANA_WINDOW = 00±3%±4%±5%
Voltage window, VANA_WINDOW = 01±4%±5%±6%
Voltage window, VANA_WINDOW = 10 or 11±9%±10%±11%
VMON1 and VMON2 Voltage Monitoring ThresholdsVMONx_THRESHOLD = 0000.65V
VMONx_THRESHOLD = 0010.8
VMONx_THRESHOLD = 0101.0
VMONx_THRESHOLD = 0111.1
VMONx_THRESHOLD = 1001.2
VMONx_THRESHOLD = 1011.3
VMONx_THRESHOLD = 1101.8
VMONx_THRESHOLD = 1111.8
VMON1 and VMON2 Voltage Monitoring WindowsVMONx_WINDOW = 00, VMONx_THRESHOLD from 000 to 111±1%±2%±3%
VMONx_WINDOW = 01, VMONx_THRESHOLD from 000 to 111±2%±3%±4%
VMONx_WINDOW = 10, VMONx_THRESHOLD from 000 to 111±3%±4%±5%
VMONx_WINDOW = 11, VMONx_THRESHOLD from 000 to 111±5%±6%±7%
Buck0 and Buck1 Voltage Monitoring WindowsBUCKx_WINDOW = 00±20±30±40mV
BUCKx_WINDOW = 01±37±50±63
BUCKx_WINDOW = 10±57±70±83
BUCKx_WINDOW = 11±77±90±103
Boost Voltage MonitoringBOOST_WINDOW = 00±0.6%±2%±3.4%
BOOST_WINDOW = 01±2.6%±4%±5.4%
BOOST_WINDOW = 10±4.6%±6%±7.4%
BOOST_WINDOW = 11±6.6%±8%±9.4%
Deglitch timeVANA, VMONx and BOOST monitoring1217μs
BUCKx monitoring69
PROTECTION FUNCTIONS
Thermal warning Temperature rising, TDIE_WARN_LEVEL = 0 115 125 135 °C
Temperature rising, TDIE_WARN_LEVEL = 1130140150
Hysteresis20
Thermal shutdownTemperature rising140150160°C
Hysteresis20
VANAOVPVANA OvervoltageVoltage rising, VANA_OVP_SEL = 05.65.86.1V
Voltage falling, VANA_OVP_SEL = 05.455.735.96
Voltage rising, VANA_OVP_SEL = 14.14.34.6
Voltage falling, VANA_OVP_SEL = 13.954.234.46
Hysteresis40200mV
VANAUVLOVANA Undervoltage LockoutVoltage rising2.512.632.75V
Voltage falling2.52.62.7
BUCKx short circuit detectionThreshold0.320.350.45V
Bypass short circuit current limit270420mA
LOAD CURRENT MEASUREMENT FOR BUCK CONVERTERS
Current measurement rangeCurrent corresponding to maximum output code (note: maximum current for LP87702 buck is 3.5A)10.22A
ResolutionLSB20mA
Measurement accuracyIOUT > 1A<10%
Measurement timeAuto mode (automatically changing to PWM mode for the measurement)50µs
PWM mode25
CURRENT CONSUMPTION
Shutdown current consumptionNRST = 01µA
Standby current consumption, converters disabledNRST = 19µA
Active current consumption, one buck converter enabled in Auto mode, internal RC oscillatorIOUT_Bx = 0 mA, not switching55µA
Active current consumption, two buck converters enabled in Auto mode, internal RC oscillatorIOUT_Bx = 0 mA, not switching90µA
Active current consumption during PWM operation, one buck converter enabledIOUT_Bx = 0 mA15mA
Active current consumption during PWM operation, two buck converters enabledIOUT_Bx = 0 mA27mA
Active current consumption, Boost converter in PWM operationIOUT_BST = 0 mA, fSW = 4 MHz18mA
PLL and clock detector current consumptionAdditional current consumption when enabled, 2 MHz external clock2mA
DIGITAL INPUT SIGNALS SCL, SDA, NRST, EN1, EN2, EN3, CLKIN,
WDI
VILInput low level0.4V
VIHInput high level1.2
VHYSHysteresis of Schmitt Trigger inputs1080200mV
ENx, CLKIN, WDI pull-down resistanceENx_PD = 1, CLKIN_PD = 1, WDI_PD = 1500kΩ
NRST pull-down resistanceAlways enabled500kΩ
DIGITAL OUTPUT SIGNALS nINT, SDA
VOLOutput low levelSDA: ISOURCE = 20 mA0.5V
nINT: ISOURCE = 2 mA0.4
RPExternal pull-up resistor for nINTTo VIO Supply10kΩ
DIGITAL OUTPUT SIGNALS PGOOD, PG1, GPO0, GPO1, GPO2,
WD_RESET
VOLOutput low levelISOURCE = 2 mA0.4V
VOHOutput high level, configured to push-pullISINK = 2 mAVVANA - 0.4VVANA
VPUSupply voltage for external pull-up resistor, configured to open-drainVVANA
RPUExternal pull-up resistor, configured to open-drain10kΩ
ALL DIGITAL INPUTS
ILEAKInput currentAll logic inputs except NRST, over pin voltage range, when PD not enabled−11µA
NRST, over pin voltage range. Other logic inputs when PD enabled.–120µA
(1) All voltage values are with respect to network ground.
(2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis.
(3) The maximum output current can be limited by the forward current limit ILIM FWD. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.
(4) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current. Applies when internal oscillator is used.
(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and the inductor current level.
(6) The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.