Examples of a proper layout for boost, buck-boost,
and buck, topology of the LP885 family are shown below.
- Creating a large GND plane for good electrical and thermal performance is important.
- Confirm that the IN and GND traces are as wide as possible to reduce trace
impedance. Wide traces have the additional advantage of providing excellent heat
dissipation.
- Use thermal vias to connect the top-side GND plane to additional
printed-circuit board (PCB) layers for heat dissipation and grounding.
- Locate the input capacitors as close as possible to the IN pin and the GND
pin.
- Place the VCC capacitor as close as possible to
VCC pin to provide stable LDO output voltage.
- Verify that the SW trace remains as short as possible to reduce parasitic
inductance and thereby reduce transient voltage spikes. Short SW trace also
reduces radiated noise and EMI.
- Do not allow switching current to flow under the device.
- The routing of CSN and CSP traces are recommended to be in parallel and kept as
short as possible and placed away from the high-voltage switching trace and the
ground shield.
- Place the compensation capacitor as close as possible to COMP pin to prevent
oscillation and system instability.