SLVSH05A November 2023 – August 2025 LP8865U-Q1 , LP8865V-Q1 , LP8865W-Q1 , LP8865X-Q1 , LP8865Y-Q1 , LP8865Z-Q1
PRODUCTION DATA
The PWM dimming mode is enabled when the ADIM/HD input pin is always high and the PWM/EN input pin is configured by a PWM input signal. Device supports PWM input signals with ultra-narrow pulse width down to 200ns in PWM dimming mode. The input duty cycle can be changed in the opposite direction only when duty cycle changes by more than 0.38% in hybrid dimming.
In PWM dimming mode, when the PWM input signal at the PWM pin turns from low to high, the internal NMOS FET starts switching and the inductor current rises to the determined value. The LED current is then regulated at the determined value, as long as the PWM input signal remains high. When the PWM input signal turns from high to low, the internal FET is turned off, causing the inductor current to fall to zero. The internal FET remains off and the LED current remains at zero if the PWM input signal stays low.