The materials used in manufacturing the REF50xx have differing coefficients of thermal expansion, resulting in stress on the device die when the part is heated. Mechanical and thermal stress on the device can cause the output voltages to shift, degrading the initial accuracy and drift specifications of the product. Reflow soldering is a common cause of this error.

To illustrate this effect, 36 devices are soldered on printed-circuit-boards using lead-free solder paste and the paste manufacturer suggested reflow profile. Figure 7-1 shows the reflow profile. The printed-circuit-board is comprised of FR4 material. The board thickness is 0.8mm and the area is 13mm × 13mm.

The reference voltage is measured before and after the reflow process across temperature; the typical shift of accuracy and drift is displayed in Figure 7-2 for REF50xxEI and Figure 7-3 through Figure 7-10 for REF50xx. Although all tested units exhibit very low shifts, higher shifts are also possible depending on the size, thickness, and material of the printed-circuit-board. An important note is that the histograms display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is common on printed circuit boards (PCBs) with surface-mount components on both sides, causes additional shifts in the output bias voltage. If the PCB is exposed to multiple reflows, then solder the device in the last pass to minimize device exposure to thermal stress.

Figure 7-1 Reflow Profile

Figure 7-2 Solder Heat Shift Distribution (%), REF50xxEI

Figure 7-3 Solder Heat Shift Distribution (%), SOIC Package

Figure 7-5 Drift Pre-Soldering Distribution, SOIC Package

Figure 7-7 Drift Distribution Pre-Soldering, VSSOP Package

Figure 7-9 Drift Shift Distribution, SOIC Package

Figure 7-4 Solder Heat Shift Distribution (%), VSSOP Package

Figure 7-6 Drift Post Soldering Distribution, SOIC Package

Figure 7-8 Drift Distribution Post-Soldering, VSSOP Package

Figure 7-10 Drift Shift Distribution, VSSOP Package