SLLSEV0E November   2017  – March 2021 TCAN1043-Q1 , TCAN1043G-Q1 , TCAN1043H-Q1 , TCAN1043HG-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings IEC Specification
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Dissipation Ratings
    7. 7.7 Electrical Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Internal and External Indicator Flags (nFAULT and RXD)
      2. 9.3.2 Power-Up Flag (PWRON)
      3. 9.3.3 Wake-Up Request Flag (WAKERQ)
      4. 9.3.4 Wake-Up Source Recognition Flag (WAKESR)
      5. 9.3.5 Undervoltage Fault Flags
        1. Undervoltage on VCC Fault
        2. Undervoltage on VIO Fault
        3. Undervoltage on VSUP Fault
      6. 9.3.6 CAN Bus Failure Fault Flag
      7. 9.3.7 Local Faults
        1. TXD Dominant Timeout (TXD DTO)
        2. TXD Shorted to RXD Fault
        3. CAN Bus Dominant Fault
        4. Thermal Shutdown (TSD)
        5. RXD Recessive Fault
        6. Undervoltage Lockout (UVLO)
        7. Unpowered Device
        8. Floating Terminals
        9. CAN Bus Short Circuit Current Limiting
    4. 9.4 Device Functional Modes
      1. 9.4.1 CAN Bus States
      2. 9.4.2 Normal Mode
      3. 9.4.3 Silent Mode
      4. 9.4.4 Standby Mode
      5. 9.4.5 Go-to-Sleep Mode
      6. 9.4.6 Sleep Mode with Remote Wake and Local Wake Up Requests
        1. Remote Wake Request via Wake Up Pattern (WUP)
        2. Local Wake Up (LWU) via WAKE Input Terminal
      7. 9.4.7 Driver and Receiver Function Tables
      8. 9.4.8 Digital Inputs and Outputs
      9. 9.4.9 INH (Inhibit) Output
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. Bus Loading, Length and Number of Nodes
      2. 10.2.2 Detailed Design Procedures
        1. CAN Termination
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout
      1. 12.1.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • DMT|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

  • Place the protection and filtering circuitry close to the bus connector to prevent transients, ESD and noise from propagating onto the board. In this layout example a transient voltage suppression (TVS) device, D1, has been shown as added protection. The production solution can be either bi-directional TVS diode or varistor with ratings matching the application requirements. This example also shows optional bus filter capacitors C6 and C8. Additionally (not shown) a series common mode choke (CMC) can be placed on the CANH and CANL lines between the TCAN1043xx-Q1 transceiver and the connector.
  • Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device.
  • Use supply (VCC) and ground planes to provide low inductance as high-frequency current will follow the path of least impedance and not the path of least resistance.
  • Use at least two vias for supply (VCC, VIO, VSUP) and ground connections of bypass capacitors and protection devices to minimize trace and via inductance.
  • Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver, examples are C4 on the VCC supply net, C5 on the VIO supply net and C9 on the VSUP supply net.
  • Bus termination: this layout example shows split termination. This is where the termination is split into two resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C7. Split termination provides common mode filtering for the bus. When bus termination is placed on the board instead of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the bus thus also removing the termination. See the application section for information on power ratings needed for the termination resistor(s).
  • To limit current of digital lines, series resistors may be used as in R2, R3 and R5 but are not required.
  • Terminal 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used, this is mandatory to ensure the bit timing into the device is met.
  • Terminal 9: SW1 is oriented in a low-side configuration which is used to implement a local WAKE event. The series resistor R10 is needed for protection against over current conditions as it limits the current into the WAKE pin when the ECU has lost its ground connection. The pull-up resistor R9 is required to provide sufficient current during stimulation of a WAKE event. See the application section for more information on calculating both the R9 and R10 values.
  • Terminal 14: Is shown assuming the mode terminal, nSTB, is used. If the device is only be used in normal mode, R5 is not needed and R4 could be used for the pull-up resistor to VIO