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Product details

Parameters

Protocols CAN Number of channels (#) 1 Supply voltage (V) 4.5 to 5.5 Bus fault voltage (V) -58 to 58 Signaling rate (Max) (Mbps) 2 Rating Automotive Operating temperature range (C) -55 to 125 Low power mode Silent, Sleep, Standby Common mode voltage (V) -30 to 30 Isolated No open-in-new Find other CAN & LIN transceivers & SBCs

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 VSON (DMT) 14 14 mm² 3 x 4.5 open-in-new Find other CAN & LIN transceivers & SBCs

Features

  • AEC Q100: Qualified for automotive applications
    • Temperature Grade 1: –55°C to 125°C, TA
    • Device HBM classification level: ±16 kV
    • Device CDM classification level: ±1500 V
  • Meets the requirements of the ISO 11898-2 (2016)
  • All devices support classic CAN and 2 Mbps CAN FD (flexible data rate) and "G" options support 5 Mbps
    • Short and symmetrical propagation delays and fast loop times for enhanced timing margin
    • Higher data rates in loaded CAN networks
  • VIO Level shifting supports 2.8 V to 5.5 V
  • Operating modes
    • Normal mode
    • Standby Mode with INH output and local and remote wake up request
    • Low power sleep mode with INH output and local and remote wake up request
  • Ideal passive behavior when unpowered
    • Bus and logic terminals are high impedance (no load to operating bus or application)
    • Hot plug capable: power up/down glitch free operation on bus and RXD output
  • Meets or exceeds EMC standard requirements
    • IEC 62228-3 – 2007 compliant
    • SAE J2962-2 compliant
  • Protection features
    • IEC ESD protection of bus terminals: ±8 kV
    • Bus fault protection: ±58 V (non-H variants) and ±70 V (H variants)
    • Undervoltage protection on supply terminals
    • Driver dominant time Out (TXD DTO): data rates down to 9.2 kbps
    • Thermal shutdown protection (TSD)
  • Receiver common mode input voltage: ±30 V
  • Typical loop delay: 110 ns
  • Junction temperatures from –55°C to 150°C
  • Available in SOIC (14) package and leadless VSON (14) package (4.5 mm x 3.0 mm) with improved automated optical inspection (AOI) capability

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Description

The TCAN1043xx-Q1 meets the physical layer requirements of the ISO 11898–2 (2016) High Speed Controller Area Network (CAN) specification providing an interface between the CAN bus and the CAN protocol controller. These devices support both classical CAN and CAN FD up to 2 megabits per second (Mbps). Devices with part numbers that include the suffix “G” are designed for CAN FD data rates up to 5 Mbps. The TCAN1043xx-Q1 allows for system-level reductions in battery current consumption by selectively enabling (via the INH output pin) the various power supplies that may be present on a node. This allows an ultra-low-current sleep state in which power is gated to all system components except for the TCAN1043xx-Q1, which remains in a low-power state monitoring the CAN bus.

When a wake-up pattern is detected on the bus or when a local wake-up is requested via the WAKE input, the TCAN1043xx-Q1 will initiate node start-up by driving INH high. The TCAN1043xx-Q1 includes internal logic level translation via the VIO terminal to allow for interfacing directly to 3.3 V or 5 V controllers. The device includes many protection and diagnostic features including CAN bus line short-circuit detection and battery connection detection. The TCAN1043xx-Q1 meets the ESD and EMC requirements of IEC 62228-3 and J2962-2 without the need for additional protection components.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 4
Type Title Date
* Datasheet TCAN1043xx-Q1 Low-Power Fault Protected CAN Transceiver with CAN FD and Wake datasheet (Rev. D) Jul. 23, 2019
Functional safety information TCAN1043-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA Jul. 30, 2020
Application note TPS65313-Q1 and TPS65653-Q1 LDO free power solution for AWR1642/AWR1843 Jan. 27, 2020
User guide TCAN1043HG-Q1 Evaluation Module Oct. 30, 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
49
Description

The TI TCAN1043HG-Q1 EVM helps designers evaluate the operation and performance of the TCAN1043HG-Q1 CAN FD transceiver. The ability to perform system-level evaluation using the VIO, EN, INH, nSTB, VSUP, WAKE, and nFAULT pins can be realized on the EVM. It also provides bus termination, bus (...)

Features
  • Easy access to all pins of the CAN transceiver
  • Pads provided for common protection/filtering components
  • Termination can be selectively enabled via jumpers

Design tools & simulation

SIMULATION MODEL Download
SLLM394.ZIP (52 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

Reference designs

REFERENCE DESIGNS Download
Automotive domain controller for gateway, assisted and automated driving systems reference design
TIDEP-01020 Decentralized vehicle architectures on the road today use individual ECUs that lack processing power and high-speed interfaces to handle the complex tasks and data movement needs of newly emerging automotive architectures. Higher level functions require the right combination of DMIPS, data bandwidth (...)
document-generic Schematic
REFERENCE DESIGNS Download
Cost-optimized digital cluster automotive reference design with Jacinto™ automotive processor
TIDEP-01002 The Jacinto™ automotive processor Digital Cluster Automotive Reference Design (DCARD) is a cost-optimized design for reconfigurable digital cluster systems.  DCARD is a complete and self-contained 6-layer PCB design to enable 60fps digital cluster solutions on 1920x720 resolution displays (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SOIC (D) 14 View options
VSON (DMT) 14 View options

Ordering & quality

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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