SLLSEV0E November   2017  – March 2021 TCAN1043-Q1 , TCAN1043G-Q1 , TCAN1043H-Q1 , TCAN1043HG-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings IEC Specification
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Dissipation Ratings
    7. 7.7 Electrical Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Internal and External Indicator Flags (nFAULT and RXD)
      2. 9.3.2 Power-Up Flag (PWRON)
      3. 9.3.3 Wake-Up Request Flag (WAKERQ)
      4. 9.3.4 Wake-Up Source Recognition Flag (WAKESR)
      5. 9.3.5 Undervoltage Fault Flags
        1. 9.3.5.1 Undervoltage on VCC Fault
        2. 9.3.5.2 Undervoltage on VIO Fault
        3. 9.3.5.3 Undervoltage on VSUP Fault
      6. 9.3.6 CAN Bus Failure Fault Flag
      7. 9.3.7 Local Faults
        1. 9.3.7.1 TXD Dominant Timeout (TXD DTO)
        2. 9.3.7.2 TXD Shorted to RXD Fault
        3. 9.3.7.3 CAN Bus Dominant Fault
        4. 9.3.7.4 Thermal Shutdown (TSD)
        5. 9.3.7.5 RXD Recessive Fault
        6. 9.3.7.6 Undervoltage Lockout (UVLO)
        7. 9.3.7.7 Unpowered Device
        8. 9.3.7.8 Floating Terminals
        9. 9.3.7.9 CAN Bus Short Circuit Current Limiting
    4. 9.4 Device Functional Modes
      1. 9.4.1 CAN Bus States
      2. 9.4.2 Normal Mode
      3. 9.4.3 Silent Mode
      4. 9.4.4 Standby Mode
      5. 9.4.5 Go-to-Sleep Mode
      6. 9.4.6 Sleep Mode with Remote Wake and Local Wake Up Requests
        1. 9.4.6.1 Remote Wake Request via Wake Up Pattern (WUP)
        2. 9.4.6.2 Local Wake Up (LWU) via WAKE Input Terminal
      7. 9.4.7 Driver and Receiver Function Tables
      8. 9.4.8 Digital Inputs and Outputs
      9. 9.4.9 INH (Inhibit) Output
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length and Number of Nodes
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Termination
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout
      1. 12.1.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • DMT|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
SUPPLY CHARACTERISTICS
ISUPSupply current
VSUP
Normal, Silent, Go-to-Sleep4070µA
Standby modeStandby mode, VCC > 4.5 V, VIO > 2.8 V,
VINH = V(WAKE) = VSUP
1545µA
Sleep modeSleep mode, VCC = VIO = VINH = 0 V
V(WAKE) = VSUP
1530µA
ICCSupply current
Normal mode
VCC
DominantSee Figure 8-2. TXD = 0 V, RL = 60 Ω, CL = open. Typical bus load.70mA
See Figure 8-2. TXD = 0 V, RL = 50 Ω, CL = open. High bus load.80mA
Dominant with bus faultSee Figure 8-2. TXD = 0 V, CANH = -25 V, RL = open, CL = open
110mA
RecessiveSee Figure 8-2. TXD = VIO, RL = 50 Ω, CL = open, RCM = open5mA
Supply current Silent and Go-to-Sleep modeSee Figure 8-2. TXD = VIO, RL = 50 Ω, CL = open2.5mA
Supply current Standby modeSee Figure 8-2. EN = L, NSTB = L5µA
Sleep modeSee Figure 8-2. EN = H or L, NSTB = L5
IIOI/O supply currentNormal modeRXD floating, TXD = 0 V (dominant) nSTB = VIO, EN = VIO450µA
Normal, Silent or Go-to-Sleep modeRXD floating, TXD = VIO recessive5µA
µA
Sleep modeNSTB = L5µA
UVSUPUndervoltage detection on VSUP for protected mode3.04.2V
VHYS(UVSUP)Hysteresis voltage on UVSUP50mV
UVVCCRising undervoltage detection on VCC for protected mode4.14.4V
Falling undervoltage detection on VCC for protected mode3.53.9V
VHYS(UVVCC)Hysteresis voltage on UVVCC200mV
UVVIOUndervoltage detection on VIO for protected mode1.32.75V
VHYS(UVIO) Hysteresis voltage on UVIO80mV
Driver Electrical Characteristics
VO(D)Bus output voltage
dominant - normal mode
CANHSee Figure 8-2 and Figure 9-3, TXD = 0 V, Normal mode, 50 ≤ RL ≤ 65 Ω, CL = open, RCM = open2.754.5V
CANL0.52.25V
VO(R)Bus output voltage
recessive
CANH and CANLSee Figure 8-2 and Figure 9-3, TXD = VCC, VIO = VCC, Normal or Silent(2), RL = open, RCM = open20.5 × VCC3V
VOD(D)Differential output voltage dominantCANH - CANLSee Figure 8-2 and Figure 9-3, TXD = 0 V, Normal mode, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open1.53V
See Figure 8-2 and Figure 9-3, TXD = 0 V, Normal mode, 45 Ω ≤ RL ≤ 50 Ω, CL = open, RCM = open1.43V
See Figure 8-2 and Figure 9-3, TXD = 0 V, Normal mode, RL = 2240 Ω, CL = open, RCM = open1.55V
See Figure 8-2 and Figure 9-3, TXD = 0 V, Normal mode, 45 Ω ≤ RL ≤ 70 Ω, CL = open, RCM = open1.43.3V
VOD(R)Differential output voltage recessiveCANH - CANLSee Figure 8-2 and Figure 9-3, TXD = VCC, Normal or Silent mode(2), RL = 60 Ω, CL = open, RCM = open–12012mV
See Figure 8-2 and Figure 9-3, TXD = VCC, Normal or Silent mode(2), RL = open, CL = open, RCM = open–5050mV
VSYMDriver symmetry, dominant or recessive
VSYM = (VO(CANH) + VO(CANL))/VCC
See Figure 8-2 and Figure 10-4, Normal mode, CL = open, RCM = open, TXD = 1MHz(3)0.91.1V / V
VSYM_DCDriver symmetry, dominant
VSYM(DC) = VCC - VO(CANH) - VO(CANL)
See Figure 8-2 and Figure 9-3, Normal or Silent mode, RL = 60 Ω, CL = open, RCM = open–400400mV
IOS(DOM)Short circuit steady-state output current
dominant
See Figure 8-10 and Figure 9-3, VCANH = -5 V, CANL = open, TXD = 0 V–100mA
See Figure 8-10 and Figure 9-3, VCANL = 40 V, CANH = open, TXD = 0 V100mA
IOS(REC)Short circuit steady-state output current
recessive
See Figure 8-10 and Figure 9-3
–27 V ≤ VBUS ≤ 32 V, VBUS = CANH = CANL, TXD = VIO
–55mA
VO(STB)Bus output voltage
Standby mode
CANHSTB = VCC or VIO, RL = open,
RCM = open
–0.100.1V
CANL–0.100.1V
CANH - CANL–0.200.2V
Receiver Electrical Characteristics
VCMCommon mode range
Normal and Silent modes
See Figure 8-3 and Table 9-5-3030V
VITInput threshold voltage
Normal and Silent modes
See Figure 8-3 and Table 9-5, VCM ≤ ±20 V500900mV
See Figure 8-3 and Table 9-5, VCM ≤ ±30 V4001000mV
VRECReceiver recessive voltageSee Figure 8-3 and Table 9-5
Normal or Silent mode, VCM = ±20V
-30.5V
VDOMReceiver dominant voltage0.98V
VHYSHysteresis voltage for input threshold
Normal and Silent modes
See Figure 8-3 and Table 9-5120mV
VIT(Sleep)Input threshold
Sleep mode
See Figure 8-3 and Table 9-5; VCM = ±124001150mV
VREC(Sleep)Receiver recessive voltage
Sleep mode
-30.4V
VDOM(Sleep)Receiver dominant voltage
Sleep mode
1.158V
VCMCommon mode range
Standby, Go-to-Sleep and Sleep modes
See Figure 8-3 and Table 9-5-1212V
IIOFF(LKG)Power-off (unpowered) bus input leakage currentCANH = CANL = 5 V, VCC = GND, VIO = GND, VSUP = 0 V4.8µA
CIInput capacitance to ground (CANH or CANL)TXD = VCC, VIO = VCC(4)2430pF
CIDDifferential input capacitance (CANH or CANL)1215pF
RIDDifferential input resistanceTXD = VCC = VIO = 5 V, Normal mode; -30 ≤ VCM ≤ +30V3080kΩ
RINInput resistance (CANH or CANL)1540kΩ
RIN(M)Input resistance matching:
[1 – RIN(CANH) / RIN(CANL)] × 100%
V(CANH) = V(CANL) = 5V–2%2%
RCBF Valid differential load impedance range for bus fault circuitryRCM = RL, CL = open4570Ω
TXD TERMINAL (CAN TRANSMIT DATA INPUT)
VIHHigh level input voltage0.7 VIOV
VILLow level input voltage0.3 VIOV
IIHHigh level input leakage currentTXD = VCC = VIO = 5.5 V–2.501µA
IILLow level input leakage currentTXD = 0 V, VCC = VIO = 5.5 V–100–2.5µA
ILKG(OFF)Unpowered leakage currentTXD = 5.5 V, VCC = VIO = 0 V–101µA
CIInput capacitanceVIN = 0.4 x sin(2 x π x 2 x 106 x t) + 2.5 V
5pF
RXD TERMINAL (CAN RECEIVE DATA OUTPUT)
VOHHigh level output voltageSee Figure 8-3, IO = –2 mA.0.8 VIOV
VOLLow level output voltageSee Figure 8-3, IO = –2 mA.0.2 VIOV
nFAULT TERMINAL (FAULT AND STATUS OUTPUT)
VOHHigh level output voltageSee Figure 8-1, IO = –2 mA.0.8 VIOV
VOLLow level output voltageSee Figure 8-1 IO = 2 mA.0.2 VIOV
nSTB TERMINAL (STANDBY MODE INPUT)
VIHHigh level input voltage0.7 VIOV
VILLow level input voltage0.3 VIOV
IIHHigh level input leakage currentnSTB = VCC = VIO = 5.5 V0.510µA
IILLow level input leakage currentnSTB = 0 V, VCC = VIO = 5.5 V–11µA
ILKG(OFF)Unpowered leakage currentnSTB = 5.5 V, VCC = 0V, VIO = 0 V–101µA
EN TERMINAL (ENABLE MODE INPUT)
VIHHigh level input voltage0.7 VIOV
VILLow level input voltage0.3 VIOV
IIHHigh level input leakage currentEN = VCC = VIO = 5.5 V0.510µA
IILLow level input leakage currentEN = 0 V, VCC = VIO = 5.5 V–11µA
ILKG(OFF)Unpowered leakage currentEN = 5.5 V, VCC = 0V, VIO = 0 V–101µA
INH TERMINAL (INHIBIT OUTPUT)
ΔVHHigh level voltage drop INH with respect to VSUPIINH = –0.5 mA0.51V
ILKG(INH)Leakage currentINH = 0 V, Sleep Mode-55µA
Wake TERMINAL (WAKE INPUT)
VIHHigh level input voltageStandby and Sleep ModeVSUP - 1.9V
VILLow level input voltageStandby and Sleep ModeVSUP - 3.5V
IIHHigh level input current(5)WAKE = VSUP – 1 V–25–15µA
IILLow level input current(5)WAKE = 1 V1525µA
All typical values are at 25°C and supply voltages of VCC = 5 V, VIO = 3.3 V, and RL = 60 Ω. Unless otherwise noted.
The recessive bus voltage will be the same if the device is in Normal mode with the nSTB and EN terminals high or if the device is in Silent mode with the nSTB terminal high and EN terminal low.
The bus output voltage symmetry, VSYM, is measured using RTERM / 2 = 30 Ω and CSPLIT = 4.7 nF as shown in Figure 10-4
Specified by design and verified during product validation using the ISO 11898-2 method.
To minimize system level current consumption, the WAKE pin will automatically configure itself based on the applied voltage to have
either an internal pull-up or pull-down current source. A high level input results in an internal pull-up and a low level input results in an
internal pull-down. For more information, refer to Section 10.4.6.2