SLLSEV0E November   2017  – March 2021 TCAN1043-Q1 , TCAN1043G-Q1 , TCAN1043H-Q1 , TCAN1043HG-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings IEC Specification
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Dissipation Ratings
    7. 7.7 Electrical Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Internal and External Indicator Flags (nFAULT and RXD)
      2. 9.3.2 Power-Up Flag (PWRON)
      3. 9.3.3 Wake-Up Request Flag (WAKERQ)
      4. 9.3.4 Wake-Up Source Recognition Flag (WAKESR)
      5. 9.3.5 Undervoltage Fault Flags
        1. Undervoltage on VCC Fault
        2. Undervoltage on VIO Fault
        3. Undervoltage on VSUP Fault
      6. 9.3.6 CAN Bus Failure Fault Flag
      7. 9.3.7 Local Faults
        1. TXD Dominant Timeout (TXD DTO)
        2. TXD Shorted to RXD Fault
        3. CAN Bus Dominant Fault
        4. Thermal Shutdown (TSD)
        5. RXD Recessive Fault
        6. Undervoltage Lockout (UVLO)
        7. Unpowered Device
        8. Floating Terminals
        9. CAN Bus Short Circuit Current Limiting
    4. 9.4 Device Functional Modes
      1. 9.4.1 CAN Bus States
      2. 9.4.2 Normal Mode
      3. 9.4.3 Silent Mode
      4. 9.4.4 Standby Mode
      5. 9.4.5 Go-to-Sleep Mode
      6. 9.4.6 Sleep Mode with Remote Wake and Local Wake Up Requests
        1. Remote Wake Request via Wake Up Pattern (WUP)
        2. Local Wake Up (LWU) via WAKE Input Terminal
      7. 9.4.7 Driver and Receiver Function Tables
      8. 9.4.8 Digital Inputs and Outputs
      9. 9.4.9 INH (Inhibit) Output
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. Bus Loading, Length and Number of Nodes
      2. 10.2.2 Detailed Design Procedures
        1. CAN Termination
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout
      1. 12.1.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • DMT|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

CAN Bus States

The CAN bus has two logical states during operation: recessive and dominant. See Figure 9-2 and Figure 9-3.

In the recessive bus state the bus is biased to a common mode of approximately VCC/2 (2.5 V) via the high resistance internal input resistors of the receiver of each node on the bus. Recessive is equivalent to a logic high and is typically a differential voltage on the bus of approximately 0 V.

The dominant bus state is when the bus is driven differentially by one or more drivers. Current flows through the termination resistors and generates a differential voltage on the bus. Dominant is equivalent to a logic low and is a differential voltage on the bus greater than the minimum threshold for a CAN dominant. A dominant state overwrites the recessive state.

During arbitration, multiple CAN nodes may transmit a dominant bit at the same time. In this case, the differential voltage of the bus is greater than the differential voltage of a single driver.

The host microprocessor of the CAN node uses the TXD terminal to drive the bus and receives data from the bus on the RXD terminal.

The TCAN1043xx-Q1 transceivers has a third bus state in low power standby mode where the bus terminals are weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 9-2 and Figure 9-3.

GUID-A4DF0427-AC58-44A9-A0F3-AA72823F26D8-low.pngFigure 9-2 Bus States (Physical Bit Representation)
Normal and Silent Modes
Sleep and Standby Modes
Figure 9-3 Bias Unit (Recessive Common Mode Bias) and Receiver
*The enable pin can be in a logical high or low state while in sleep mode but since it has an internal pull-down, the lowest possible power consumption occurs when the pin is left either floating or pulled low externally.
Figure 9-4 State Diagram