The TCAN114x-Q1 is a CAN FD transceiver supporting data rates up to 5 Mbps meeting the high speed CAN physical layer standards: ISO 11898-2:2016. The TCAN1145-Q1 and TCAN1146-Q1 support selective wake up on dedicated CAN-frames. The devices can also wake up via remote wake up using CAN bus implementing the ISO 11898-2:2016 Wake Up Pattern (WUP). The TCAN114x-Q1 supports 1.8 V, 3.3 V and 5 V processors using VIO pin. The processor interface is through the SPI, RXD and TXD terminals. The devices have a Serial Peripheral Interface (SPI) that connects to a local microprocessor for configuration. SPI supports clock rates up to 4 MHz. The serial data output (SDO) pin can be configured as an interrupt output pin when the chip select pin is high providing flexibility for system design.
The TCAN114x-Q1 provides CAN FD transceiver function: differential transmit capability to the bus and differential receive capability from the bus. The device includes many protection features providing device and CAN network robustness.
Recessive bus state is when the bus is biased to a common mode of about 2.5 V via the high resistance internal input resistors of the receiver of each node on the bus across the termination resistors. Recessive is equivalent to logic high and is typically a differential voltage on the bus of almost 0 V. Recessive state is also the idle state.
Dominant bus state is when the bus is driven differentially by one or more drivers. Current is induced to flow through the termination resistors and generate a differential voltage on the bus. Dominant is equivalent to logic low and is a differential voltage on the bus greater than the minimum threshold for a CAN dominant. A dominant state overwrites the recessive state.
During arbitration, multiple CAN nodes may transmit a dominant bit at the same time. In this case, the differential voltage of the bus is greater than the differential voltage of a single driver.
The TCAN114x-Q1 provides many enhanced features that are provided in the Section 10.3 section. Enhanced features such as advanced bus fault detection, fail-safe, watchdog and providing a processor interrupt are described in their specific subsections.