The Serial Peripheral Interface (SPI) uses a standard configuration. Physically the digital interface pins are nCS (Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out) and SCLK (Serial Clock). Each SPI transaction is a 16, 24 or 32 bits containing an address and read/write command bit followed by one to three data bytes. Supporting two and three data bytes is accomplished utilizing burst read and write where the address is automatically incremented for the data along with the same number of clock cycles per bit. The data shifted out on the SDO pin for the transaction always starts with the Global Status Register (byte).
The SPI data input data on SDI is sampled on the low to high edge of the clock (SCLK). The SPI output data on SDO is changed on the high to low edge of the clock (SCLK).
When programming the device in sleep mode, care must be taken to understand what the output is. An example is the device is programmed with fail-safe mode off and one of the fault conditions that puts the device in sleep mode takes place, like an UVCC. While in sleep mode, fail-safe mode is enabled. the device stays in sleep mode and does not switch to fail-safe mode.