SLLS177I March   1994  – March 2021 TL16C550C

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions (Low Voltage - 3.3 nominal)
    3. 5.3  Recommended Operating Conditions (Standard Voltage - 5 V nominal)
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics (Low Voltage - 3.3 V nominal)
    6. 5.6  Electrical Characteristics (Standard Voltage - 5 V nominal)
    7. 5.7  System Timing Requirements
    8. 5.8  System Switching Characteristics
    9. 5.9  Baud Generator Switching Characteristics
    10. 5.10 Receiver Switching Characteristics
    11. 5.11 Transmitter Switching Characteristics
    12. 5.12 Modem Control Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Autoflow Control (see Figure 1-1)
    2. 7.2 Auto-RTS (see Figure 1-1)
    3. 7.3 Auto-CTS (see Figure 1-1)
    4. 7.4 Enabling Autoflow Control and Auto-CTS
    5. 7.5 Auto-CTS and Auto-RTS Functional Timing
    6. 7.6 Functional Block Diagram
    7. 7.7 Principles of Operation
      1. 7.7.1  Accessible Registers
      2. 7.7.2  FIFO Control Register (FCR)
      3. 7.7.3  FIFO Interrupt Mode Operation
      4. 7.7.4  FIFO Polled Mode Operation
      5. 7.7.5  Interrupt Enable Register (IER)
      6. 7.7.6  Interrupt Identification Register (IIR)
      7. 7.7.7  Line Control Register (LCR)
      8. 7.7.8  Line Status Register (LSR)
      9. 7.7.9  Modem Control Register (MCR)
      10. 7.7.10 Modem Status Register (MSR)
      11. 7.7.11 Programming Baud Generator
      12. 7.7.12 Receiver Buffet Register (RBR)
      13. 7.7.13 Scratch Register
      14. 7.7.14 Transmitter Holding Register (THR)
  8. 8 Application Information
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.2 FIFO Control Register (FCR)

The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.

  • Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits are written to or they are not programmed. Changing this bit clears the FIFOs.
  • Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not cleared. The 1 that is written to this bit position is self clearing.
  • Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not cleared. The 1 that is written to this bit position is self clearing.
  • Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
  • Bits 4 and 5: These two bits are reserved for future use.
  • Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 7-4).
Table 7-4 Receiver FIFO Trigger Level
BIT 7 BIT 6 RECEIVER FIFO TRIGGER LEVEL (BYTES)
0 0 01
0 1 04
1 0 08
1 1 14