SLVSJQ6 September   2025 TMF0064

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Functional Tests
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 64768-Bit FRAM
      2. 6.3.2 FRAM Status Memory
      3. 6.3.3 Address Registers and Transfer Status
      4. 6.3.4 Writing Data to the FRAM
      5. 6.3.5 TMF0064 Device ID
      6. 6.3.6 Bus Termination
    4. 6.4 Device Functional Modes
      1. 6.4.1 Test Procedures for Functional Tests
        1. 6.4.1.1 Multiple Target Configurations
    5. 6.5 Programming
      1. 6.5.1 Serial Communication
      2. 6.5.2 Initialization
      3. 6.5.3 ROM Commands
        1. 6.5.3.1 READ ROM Command [33h]
        2. 6.5.3.2 MATCH ROM Command [55h]
        3. 6.5.3.3 SKIP ROM Command [CCh]
        4. 6.5.3.4 SEARCH ROM Command [F0h]
        5. 6.5.3.5 RESUME Command [A5h]
        6. 6.5.3.6 OVERDRIVE SKIP ROM Command [3Ch]
        7. 6.5.3.7 OVERDRIVE MATCH ROM Command [69h]
      4. 6.5.4 Memory Function Commands
        1. 6.5.4.1 Write Scratchpad Command [0Fh]
        2. 6.5.4.2 Read Scratchpad Command [AAh]
        3. 6.5.4.3 Copy Scratchpad [55h]
        4. 6.5.4.4 Read Memory [F0h]
        5. 6.5.4.5 Extended Read Memory [A5h]
        6. 6.5.4.6 Memory Command Flow Charts
      5. 6.5.5 SDQ Signaling
        1. 6.5.5.1 RESET and PRESENCE PULSE
        2. 6.5.5.2 Write-Read-Time Slots
      6. 6.5.6 IDLE
      7. 6.5.7 CRC Generation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information
    2. 10.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

6.3.1 64768-Bit FRAM

Table 6-1 is a memory map of the 64768-bit FRAM section of the TMF0064 device, configured as 253 pages with 32-bytes each. Eight adjacent pages form one 256-byte block. The 32-byte volatile scratchpad buffer is used when programming the FRAM memory. The process for writing to the FRAM memory includes two steps. Data is first written to the scratchpad buffer. The data is then verified by reading the scratchpad buffer that confirms proper receipt of the data. If the buffer content is correct, a copy scratchpad command is issued to copy the scratchpad buffer to the FRAM memory. This process verifies data integrity when programming the memory. See Section 6.5.4 for details regarding programming and reading the 7680-bit FRAM portion of the TMF0064.

Table 6-1 FRAM Data Memory Map
ADDRESS RANGETYPE (1)DESCRIPTIONPROTECTION CODES (NOTES)
0000h to 00FFhR/(W)Data Memory Pages 0 to 7 (Block 0)(Protection controlled by address 1FA0h)
0100h to 01FFhR/(W)Data Memory Pages 8 to 15 (Block 1)(Protection controlled by address 1FA1h)
0200h to 02FFhR/(W)Data Memory Pages 16 to 23 (Block 2)(Protection controlled by address 1FA2h)
0300h to 03FFhR/(W)Data Memory Pages 24 to 31 (Block 3)(Protection controlled by address 1FA3h)
0400h to 04FFhR/(W)Data Memory Pages 32 to 39 (Block 4)(Protection controlled by address 1FA4h)
0500h to 05FFhR/(W)Data Memory Pages 40 to 47 (Block 5)(Protection controlled by address 1FA5h)
0600h to 06FFhR/(W)Data Memory Pages 48 to 55 (Block 6)(Protection controlled by address 1FA6h)
0700h to 07FFhR/(W)Data Memory Pages 56 to 63 (Block 7)(Protection controlled by address 1FA7h)
............
1D00h to 1DFFhR/(W)Data Memory Pages 232 to 239 (Block 29)(Protection controlled by address 1FBDh)
1E00h to 1EFFhR/(W)Data Memory Pages 240 to 247 (Block 30)(Protection controlled by address 1FBEh)
1F00h to 1F9FhR/(W)Data Memory Pages 248 to 252 (Block 31)(Protection controlled by address 1FBFh)
(1) R = Read, W = Write