SCDS457A may   2023  – june 2023 TMUX4827

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Source or Drain Continuous Current
    6. 6.6 Source or Drain RMS Current
    7. 6.7 Electrical Characteristics 
    8. 6.8 Switching Characteristics 
    9. 6.9 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  On-Leakage Current
    3. 7.3  Off-Leakage Current
    4. 7.4  Power-Off Leakage Current
    5. 7.5  Propagation Delay
    6. 7.6  tON (VDD) and tOFF (VDD) Time
    7. 7.7  Transition Time
    8. 7.8  Break-Before-Make
    9. 7.9  THD + Noise
    10. 7.10 Power Supply Rejection Ratio (PSRR)
    11. 7.11 Charge Injection
    12. 7.12 Bandwidth
    13. 7.13 Off Isolation
    14. 7.14 Crosstalk
  9. Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Device Functional Modes
    3. 8.3 Feature Description
      1. 8.3.1 Beyond the Supply
      2. 8.3.2 Bidirectional Operation
      3. 8.3.3 Over Temperature Protection
      4. 8.3.4 Power-Off Protection
      5. 8.3.5 1.8 V Logic Compatible Inputs
      6. 8.3.6 Fail-Safe Logic
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Audio Amplifier Switching
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBH|9
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self-inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 9-3 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.

GUID-DE84BF38-57F6-4115-A99B-F6EC9E9F80FC-low.gif Figure 9-3 Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies.

Some key considerations are as follows:

  • For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. TI recommends a 0.1-µF and 1-µF capacitor, placing the lowest value capacitor as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
  • Keep the input lines as short as possible.
  • Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary.
  • Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground planes.