SCPS293 November   2023 TPLD1201

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Device and Documentation Support
    1. 4.1 Receiving Notification of Documentation Updates
    2. 4.2 Support Resources
    3. 4.3 Trademarks
    4. 4.4 Electrostatic Discharge Caution
    5. 4.5 Glossary
  6. 5Revision History
  7. 6Mechanical, Packaging, and Orderable Information
    1. 6.1 Tape and Reel Information
    2. 6.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RWB|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Eight general purpose input or outputs:
    • Digital input can be configured with hysteresis, low-voltage thresholds, and internal pull-up or down resistor
    • Push-pull, open-drain (PMOS/NMOS), and Hi-Z outputs
  • Supports 1.8 V, 2.5 V, 3.3 V, and 5 V applications
  • Configurable macro-cells:
    • 2-, 3-, and 4-bit lookup tables (LUT)
    • D-type flip-flops or latches with and without reset or set option
    • Pipe delay – 8-stages, 2 outputs
    • Selectable counters or delay generators
    • Programmable deglitch filter or edge detector
    • Analog comparators – selectable VREF and input gain
    • Internal voltage reference fixed or ratiometric
    • 25 kHz and 2 MHz RC oscillator – internal divider stages
  • Extended temperature range: -40°C to 125°C
  • Development tools:
    • InterConnect Studio
    • TPLD1201 evaluation module
    • TPLD programming board