When configured as a Delay generator (DLY), this macro-cell delays the input based on counter DATA and CLK input frequency and postpones rising and/or falling edges. The initial output value of this macro-cell after device startup can also be configured to Bypass Initial, Initial Low, or Initial High. The edge on which to delay is selected by the Edge select parameter and can be configured as:

• Rising: only delay on rising edges of IN.
• Falling: only delay on falling edges of IN.
• Both: delay on both rising and falling edges of IN.

For delay applications, it is recommended to use larger counter data values for less error. If an input pulse width is shorter than the specified delay time, the pulse will be filtered out. This feature can be useful for deglitching.

If the on-chip oscillator is used, a delay error or offset is introduced depending on whether the OSC is set to "forced power on" or "auto power on". An additional 2 clock cycles are included in the delay calculation for clock synchronization with an option to bypass. Note, bypassing the clock synchronization may result in the counter resetting to an unknown value.

The delay time is calculated by DELAY = (DATA + (t_{d_err} or t_{d_os}) + 3)/f_CLK or, if 2-DFF sync is bypassed, DELAY = (DATA + (t_{d_err} or t_{d_os}) + 1)/f_CLK.

When the OSC is set to "auto power on" and DLY macro-cells are triggered subsequently before the previous output is present, the OSC will continue to clock and the DLY will begin on the next rising edge. Thus, the subsequent delays can be calculated as if the OSC were set to "forced power on".

Figure 7-11 shows an example of the Delay macro-cell operation set to both edge delay and data = 1.

Figure 7-12 shows an example timing of Delay macro-cells with respect to the edge selected and data = 3.